Abstract: A reduced cost and hardware complexity ISDN channel bank architecture supports a plurality of Basic Rate-One Transmission Extension (BRITE) ISDN circuit cards. Rather than install a dedicated processor on each BRITE card or multiple BRITE circuits on one card, each BRITE circuit card of the channel bank has no processor of its own, but is instead controlled by a shared control processor on a separate bank controller card. Since each such `processorless` BRITE circuit card contains only single BRITE circuit, removal of any one BRITE circuit card from its backplane slot will not impair the operational integrity of the other BRITE cards, so that service to customer premises equipment terminating the local loops to such cards is not interrupted. The shared processor on the bank controller card executes the same single task communication control routine for plural BRITE cards.

Abstract: The range of digital data communication services, such as a basic rate 2B1Q ISDN channel, to customer premises located beyond the industry standard achievable range of a two-wire loop can be extended by increasing the capacity of the ISDN line code from two information bits per symbol to three information bits per symbol, so as to reduce the effective symbol rate, which is error correction encoded to an effective 4B1H line code for defining a sixteen level PAM signal waveform, and employing enhanced low signal-to-noise ratio signal processing techniques in both the transmitter and receiver to accommodate the increased insertion loss of the two-wire line resulting from its extended length. Such enhanced low signal-to-noise ratio signal processing techniques include a Tomlinson precoder in the transmitter, and an adaptive linear equalizer and a module unit in the receiver.

Abstract: The problem of digital data corruption heat occurs when an analog card is inserted into a card/time slot of a D4 channel bank is effectively remedied by sampling and analyzing the channel bank's transmit enable (TNEN) lead for successive frames of time slots. Unless analyzed TNEN lead samples of a channel unit time slot of interest derived over successive frames have the same logic state associated with an analog channel unit, the PCM data lead remains default-coupled to a digital data transmission lead. This prevents PCM-encoded spurious noise on the analog PAM lead from being erroneously asserted in place of serialized digital data bits that should have been passed directly from the digital data bus to the PCM bus.

Abstract: A composite circuit card architecture conforms with a prescribed form factor for installation in a card slot and connection to a backplane of a multiple circuit card-supporting housing. Only a portion of the card is comprised of printed wiring board material, while the remainder, where no printed circuit components are installed, is a support substrate formed of a material other than that of said printed wiring board. Also, a front panel portion is formed of the material other than that of the printed wiring board, such as plastic integrally molded with the support substrate, thereby significantly reducing the cost associated with the conventional approach of making the entire card from printed circuit board material. At one communication link, such as a ribbon cable, may be coupled between the printed wiring board and at least one input/output port at the front panel.

Abstract: In order to ensure continuous telephone service to a customer premises served by an ISDN line, without requiring that the customer maintain an additional POTS line as an emergency back-up to the normally used ISDN service, ISDN signalling circuits and network termination interface components are modified, so that, in the event of a loss of power to customer premises digital communications equipment, a communication link between an auxiliary POTS telephone and the normal ISDN communication path to the central office may be established. There need not be any modification of the central office switch, per se, so that the integrity of the ISDN communication path with the central office line card remains unaffected. As a result, the central office equipment can continue to conduct standard ISDN communications with the customer premises equipment, even though the customer is employing a POTS back-up analog phone.

Abstract: A D4 channel bank data bus monitoring scheme automatically determines if a channel unit connector slot is occupied, without having to gain physical access to the interior of the channel bank cabinet and inspect the channel bank's backplane slot positions. To this end, for a respective channel unit connector slot the channel bank's transmit data bus, which is initially pulled high via a pull-up resistor, is monitored for an all `1`s state. If the data on the bus is not all `1`s, then it is inferred that a channel unit is installed. If an all `1`s state is not detected, then, during the next time slot for that channel unit, the bus is decoupled from the pull-up resistor and coupled instead to a `soft` pull-down resistor. If the data on the bus is now all `0`s, it is inferred that the previously read all `1`s condition was due to the fact that no channel unit is installed, and the channel unit connector slot is declared as empty.

Abstract: The transmission distance for DDS subscriber lines over a repeaterless four-wire link is extended to customer premises beyond the standard four-wire loop range of approximately 18 kft (56 kbps, 56 kbps with secondary channel capability, and 64 kbps) by employing commercially available ISDN transceiver chip hardware to multiplex a DDS data channel into quarter-rate (2B1Q) ISDN channels. At least one of a signalling channel and an out-of-band maintenance channel is used to convey differential delay compensation information, without modifying the framing structure of the transported channels, or requiring additional bandwidth for a separate framing channel.

Abstract: Controlled activation of a message-waiting light of a telephone unit of a PBX system, that is coupled over a two-wire link to a foreign exchange subscriber circuit terminating a digital communication link, is carried out by hardware and software modifications to each of FXO and FXS channel units at opposite ends of the digital communication link. These modifications are effective to rob redundant signalling bits of extended superframe format time division multiplexed digital communication signals to transport a prescribed request code, that instructs the FXS circuit to generate a message-waiting light driving signal on the tip-ring pair to the message-waiting phone.

Abstract: A local subscriber loop architecture embeds digitized POTS signals into the framing format of high bit rate digital subscriber loop signals being transported over a local loop for serving both subscriber digital terminal equipment and a POTS telephone. The remote transceiver unit is line-powered from the central office unit, facilitating installation of a reliable (office-powered) POTS interface (containing codec and subscriber line interface circuitry providing BORSHT functions) into the remote unit. The data rate of the added digital POTS signal is relatively small with respect to the data rate of the DSL channels, so that there is only slight increase in the overall data rate. As a consequence, adding the digital POTS signal has negligible impact on transport range.

Abstract: An ISDN terminal adapter is capable of providing both digital and analog communication connectivity between a customer's data terminal equipment (DTE) and a digital communication link. The adapter includes a digital (ISDN) communication transceiver for transmitting and receiving digital communication signals on the ISDN link. A first digital communication connector is coupled with the DTE. A second digital communication connector is coupled with the customer's modem. An analog communication connector is coupled with an analog port of the modem. An analog/digital communication interface is coupled between the analog communication connector and the digital communication transceiver. A serial communication exchange processor is coupled with the first and second digital communication connectors and the transceiver.

Abstract: A sub (half)-rate DDS channel transport network architecture is configured to drive each of a ISDN transceiver unit of an OCU DP at one end of a two-wire path and the ISDN transceiver unit of a DDS termination unit at an opposite end of the two-wire path at one-half the normal clock rate, which reduces the operating frequency for rates of 56 kbps and 64 kbps. This sub-rate operation decreases its vulnerability to interference sources such as bridge taps. It also offers a trade-off against loop loss, enabling the effective range of the two-wire DDS circuit to be geographically extended, while complying with applicable industry standards for loop deployment and testing.

Abstract: A limited search variant of the fixed delay tree search detector is used to recover digital signals corrupted with intersymbol interference and additive noise. The limited search algorithm uses a variant of an equalizer decision device--a simple slicer--to reduce the number of paths that are considered by the tree search detector from M.sup.D+1 to either D+1 or 2.sup.D+1 paths, thereby significantly reducing the complexity of the tree-search detector. This limited search detector enjoys negligible loss in performance, compared with that of a full fixed delay tree search.

Abstract: In order to transport digital data across a reliable digital communication link from a transmit site to a destination site, the data is processed in parallel paths to derive error detection information, such as a cyclic redundancy code, and to encode the data. The outputs of the parallel paths are combined into a composite digital data sequence, which is then transmitted over the reliable digital communication link to the destination site. At the destination site, the encoded digital data component of the composite data sequence is decoded and then subjected to the same error detection operation carried out at the transmit site to derive error detection information associated with the decoded digital data. This recalculated error detection information is compared with the error detection information component contained in the composite digital data sequence. If there is a mismatch, the reliable digital communication link and the encoder at the transmit site and the decoder at the destination site are reset.

Abstract: A transmission strobe clock signal control mechanism continuously monitors DTE data and transmission strobe clock signals used to strobe the DTE data onto a serial communication link, and automatically adjusts the phase of the transmission strobe clock signal in response to a misalignment between the two signals that exceeds acceptable limits. In a first embodiment, the DTE data signal is sampled by a high speed clock and clocked through a `data sample` shift register. Selected stages of the register, associated with a timing window that contains a transmission strobe clock signal edge, are coupled to an exclusive logic operation circuit, whose output indicates whether all of the data samples in the selected stages of the shift register are the same or not. If not, it is inferred that a data transition too close to the transmission strobe clock signal edge has occurred, necessitating an adjustment of the phase of the transmission strobe clock signal.

Abstract: A line driver with positive feedback reduces the output signal amplitude excursion required for driving a communication line, and enables the driver's output impedance to be synthesized using a reduced component value, thereby achieving a reduction in power loss through the output resistor, while simultaneously matching the effective electrical value of the driver's output impedance to the line. The line driver includes an operational amplifier having differential polarity inputs and an output. An output resistor, whose value is a fraction of the line impedance, is coupled between the amplifier output and an output node coupled to the line. A negative feedback resistor is coupled between the amplifier output and an inverting input. A further resistor is coupled between the amplifier output and a non-inverting input.

Abstract: A performance monitoring arrangement conducts auxiliary communications between a performance-monitoring capable line interface unit and one or more performance-monitoring capable channel units of a D4 channel bank without interrupting transmission of digital data to and from a customer premises. During each of an initialization mode and a performance-monitoring mode, the data communication format of a channel bank bus is modified to allow insertion of an auxiliary line interface unit-sourced command bit between selected bits of the data. During the performance-monitoring mode, the communication format of the channel bank link is further modified to provide for insertion of a response bit from a channel unit and the transmission of data at an increased data rate. In the absence of an indication that there is an anomaly that would impair the operation of the channel bank, the channel unit transitions to a performance-monitoring mode of operation.

Abstract: The range of digital data communication services, such as a basic rate 2B1Q ISDN channel, to customer premises located beyond the industry standard achievable range of a two-wire loop can be extended by increasing the capacity of the ISDN line code from two information bits per symbol to three information bits per symbol, so as to reduce the effective symbol rate, which is error correction encoded to an effective 4B1H line code for defining a sixteen level PAM signal waveform, and employing enhanced low signal-to-noise ratio signal processing techniques in both the transmitter and receiver to accommodate the increased insertion loss of the two-wire line resulting from its extended length. Such enhanced low signal-to-noise ratio signal processing techniques include a Tomlinson precoder in the transmitter, and an adaptive linear equalizer and a module unit in the receiver.

Abstract: State of the art data compression-protocol engines provide high compression ratios for improving data transport over a high data rate serial communication link. However, a respective data port of data terminal equipment may not be capable of being clocked at a sufficiently high clock rate, which limits the performance of the data compression-protocol engine, and prevents full utilization of the available bandwidth of the serial link. To remedy this problem, data terminal equipment and data compression-protocol engine components that provide auxiliary data communication port connectivity are employed. Data from the data terminal equipment is clocked to the data compression-protocol engine over a plurality of parallel data paths. This increases the effective clock rate and enables the data compression-protocol engine to output a compressed data stream that fully utilizes the bandwidth of the network.

Abstract: A bandwidth-adaptive digital phase locked loop-based clock control arrangement controls the generation of a read-out clock used for retiming digital data signal interfaced with a synchronous data channel of a communication system, in which pulse-stuffing synchronization is employed to maintain clock synchronization of the digital data signal that is not bit-synchronous with a synchronous digital data channel over which the digital data signal is transported. The bandwidth-adaptive digital phase locked loop includes a loop filter to which the error signal is applied and a phase accumulator, coupled to the output of the loop filter and being operative to stepwise adjust the read-out clock signal. The loop filter has a first scaled path that includes a first, controllably stepped gain stage, and a second scaled path that includes a second, controllably stepped gain stage coupled to a frequency accumulator.

Abstract: A blank, or dummy, face plate element engages top and bottom edges of a cabinet frame, directly behind a front panel card insertion opening that provides access to multiple card slots of an electronic equipment rack. The dummy face plate includes a rearwardly projecting, upper lip, that is located adjacent to a top edge of the face plate, and has a notch immediately adjacent to the rear surface of the face plate. The notch fits within and is captured by an upper edge of the cabinet frame. A rearwardly projecting, generally U-shaped, flexible lower lip is provided adjacent to a lower edge of the face plate and includes a pair of finger grips. The flexible lower lip has a ridge that becomes aligned with the lower edge of the faceplate when the lower lip is flexed upwardly toward the first lip, and a notch adjacent to the ridge that is captured by the cabinet frame.