Abstract: A gate driver for a power MOSFET in, for example, a DC-DC converter switches the MOSFET between a fully-on condition and a low-current condition instead of switching the MOSFET between fully-on and fully-off conditions. The amount of charge that must be transferred to charge and discharge the gate of the MOSFET is thereby reduced, and the efficiency of the MOSFET is improved. A trimming process is used to adjust the magnitude of the voltage supplied by the gate driver to the gate of the power MOSFET in the low-current condition.

Abstract: An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage.

Abstract: A freewheeling MOSFET is connected in parallel with the inductor in a switched DC/DC converter. When the freewheeling MOSFET is turned on during the switching operation of the converter, while the low-side and energy transfer MOSFETs are turned off, the inductor current circulates or “freewheels” through the freewheeling MOSFET. The frequency of the converter is thereby made independent of the lengths of the magnetizing and energy transfer stages, allowing far greater flexibility in operating and converter and overcoming numerous problems associated with conventional DC/DC converters. For example, the converter may operate in either step-up or step-down mode and may even transition for one mode to the other as the values of the input voltage and desired output voltage vary.

Abstract: A DC/DC voltage converter includes an inductive switching voltage regulator and a capacitive charge pump connected in series between the input and output terminals of the converter. The charge pump has a second input terminal connected to the input terminal of the converter. This reduces the series resistance in the current path by which charge is transferred from the capacitor in the charge pump to the output capacitor and thereby improves the ability of the converter to respond to rapid changes in current required by the load.

Abstract: A cascode current sensor includes a main MOSFET and a sense MOSFET. The drain terminal of the main MOSFET is connected to a power device whose current is to be monitored, and the source and gate terminals of the main MOSFET are connected to the source and gate terminals, respectively, of the sense MOSFET. The drain voltages of the main and sense MOSFETs are equalized, in one embodiment by using a variable current source and negative feedback. The gate width of the main MOSFET is typically larger than the gate width of the sense MOSFET. Using the size ratio of the gate widths, the current in the main MOSFET is measured by sensing the magnitude of the current in the sense MOSFET. Inserting the relatively large MOSFET in the power circuit minimizes power loss.

Abstract: Devices, such as mobile devices, may be exposed to short circuit and output overload events. To protect against such events, mobile devices typically include current limit circuits. Some current limit circuits may involve user programmable function. User programmable function may need accurate current limit detectors. Various embodiments of the present invention include devices and methods for detecting one or more programmed current limits. Some embodiments allow for a user application to select among parallel or serial configurations of current detection circuitry. Each such configuration may include multiple resistive devices of different resistive values.

Abstract: Various integrated circuit devices, in particular a junction field-effect transistor (JFET), are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench. Various techniques for terminating the isolation structure by extending the floor isolation region beyond the trench, using a guard ring, and a forming a drift region are described.

Abstract: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.

Abstract: Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths.

Abstract: Processes for forming isolation structures for semiconductor devices include forming a submerged floor isolation region and a filed trench which together enclose an isolated pocket of the substrate. One process aligns the trench to the floor isolation region. In another process a second, narrower trench is formed in the isolated pocket and filled with a dielectric material while the dielectric material is deposited so as to line the walls and floor of the first trench. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.

Abstract: Exemplary systems and methods for charging a battery with a digital charge reduction loop are described herein. In some embodiments, a system comprises an exemplary digital charge reduction loop which comprises a circuit for determining a charge-current adjustment signal, a counter for generating a digital count value, and a digital-to-analog converter. The circuit for determining a charge-current adjustment signal may base the determination on a source voltage of an input source. The counter may generate a digital count value based on the charge-current adjustment signal. The digital-to-analog converter (DAC) may generate a DAC control signal based on the digital count value of the counter, the DAC control signal being representative of an amount of charge current to be used to charge a battery.

Abstract: Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths.

Abstract: A single wire serial interface for power ICs and other devices is provided. To use the interface, a device is configured to include an EN/SET input pin. A counter within the device counts clock pulses sent to the EN/SET input pin. The output of the counter is passed to a ROM or other decoder circuit. The ROM selects an operational state for the device that corresponds to the value of the counter. In this way, control states may be selected for the device by sending corresponding clock pulses to the EN/SET pin. Holding the EN/SET pin high causes the device to maintain its operational state. Holding the EN/SET pin low for a predetermined timeout period resets the counter and causes the device to adopt a predetermined configuration (such as off) until new clock pulses are received at the EN/SET pin.

Abstract: Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths.

Abstract: A soft-start voltage circuit includes an operational amplifier, a first and a second capacitors, a first and a second switches, and a voltage level shifter. The operational amplifier includes a positive end, a negative end, and an output end coupled to the negative end of the operational amplifier for outputting the soft-start voltage. The voltage level shifter is coupled between the first capacitor and the positive end of the operational amplifier for shifting a level of the voltage on the first capacitor. The first switch is coupled between the first and the second capacitors for coupling the first and the second capacitors according to the clock. The second switch is coupled between the second capacitor and the negative end of the operational amplifier for coupling the second capacitor and the negative end of the operational amplifier according to the inverted clock.

Abstract: An isolated bipolar transistor formed in a P-type semiconductor substrate includes an N-type submerged floor isolation region and a filled trench extending downward from the surface of the substrate to the floor isolation region. Together the floor isolation region and the filled trench form an isolated pocket of the substrate which contains the bipolar transistor. The collector of the bipolar transistor may comprise the floor isolation region. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.

Abstract: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.

Abstract: A PWM comprises a voltage transformation module, a voltage-sensing module and a timer. The voltage transformation module is configured to transform an input voltage into an output voltage. The voltage-sensing module is coupled to the voltage transformation module and configured to detect a voltage of a first terminal, wherein the voltage of the first terminal is proportional to the output voltage. The timer is configured to measure the time duration for which the voltage of the first terminal is lower than a reference voltage, wherein the timer initiates a short circuit signal when the time duration is greater than a predetermined value.

Abstract: A gate driver for a power MOSFET in, for example, a DC-DC converter switches the MOSFET between a fully-on condition and a low-current condition instead of switching the MOSFET between fully-on and fully-off conditions. The amount of charge that must be transferred to charge and discharge the gate of the MOSFET is thereby reduced, and the efficiency of the MOSFET is improved. A trimming process is used to adjust the magnitude of the voltage supplied by the gate driver to the gate of the power MOSFET in the low-current condition.

Abstract: A lateral MOSFET formed in a substrate of a first conductivity type includes a gate formed atop a gate dielectric layer over a surface of the substrate, a drain region of a second conductivity type, a source region of a second conductivity type, and a body region of the first conductivity type which extends under the gate. The body region may have a non-monotonic vertical doping profile with a portion located deeper in the substrate having a higher doping concentration than a portion located shallower in the substrate. The lateral MOSFET is drain-centric, with the source region and a dielectric-filled trench surrounding the drain region.