Patents Assigned to Advanced Micro Device, Inc.
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Patent number: 12105957Abstract: A memory controller includes an arbiter, a vector arithmetic logic unit (VALU), a read buffer and a write buffer both coupled to the VALU, and an atomic memory operation scheduler. The VALU performs scattered atomic memory operations on arrays of data elements responsive to selected memory access commands. The atomic memory operation scheduler is for scheduling atomic memory operations at the VALU; identifying a plurality of scattered atomic memory operations with commutative and associative properties, the plurality of scattered atomic memory operations on at least one element of an array of data elements associated with an address; and commanding the VALU to perform the plurality of scattered atomic memory operations.Type: GrantFiled: December 23, 2022Date of Patent: October 1, 2024Assignee: Advanced Micro Devices, Inc.Inventors: John Kalamatianos, Karthik Ramu Sangaiah, Anthony Thomas Gutierrez
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Publication number: 20240324248Abstract: A method for die pair partitioning can include providing a circuit die. The method can additionally include providing one or more additional circuit die having one or more fuses positioned therein, wherein the one or more fuses identify the circuit die. The method can also include connecting the one or more additional circuit die to the circuit die. Various other methods, systems, and computer-readable media are also disclosed.Type: ApplicationFiled: September 25, 2023Publication date: September 26, 2024Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: John Wuu, Kevin Gillespie, Samuel Naffziger, Spence Oliver, Rajit Seahra, Regina T. Schmidt, Raja Swaminathan, Omar Zia
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Publication number: 20240319911Abstract: One or both of read and write accesses to a fabric-attached memory module via a fabric interconnect are monitored. In one or more implementations, offloading of one or more tasks accessing the fabric-attached memory module to a processor of a routing system associated with the fabric-attached memory module is initiated based on the read and write accesses to the fabric-attached memory module. Additionally or alternatively, replicating memory of the fabric-attached memory module to a cache memory of a computing node in the disaggregated memory system executing one or more tasks of a host application is initiated based on the write accesses to the fabric-attached memory module.Type: ApplicationFiled: May 31, 2024Publication date: September 26, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Vamsee Reddy Kommareddy, SeyedMohammad SeyedzadehDelcheh, Sergey Blagodurov
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Publication number: 20240324247Abstract: A method for die pair partitioning can include providing a circuit die that has a metal stack and that includes a majority of logic transistors of an integrated circuit. The method can also include providing one or more additional circuit die that have one or more additional metal stacks of which at least one is connected to the metal stack of the circuit die and a majority of static random access memory and analog devices of the integrated circuit. The method can further include connecting at least one of the one or more additional metal stacks to the metal stack of the circuit die. Various other methods, systems, and computer-readable media are also disclosed.Type: ApplicationFiled: September 25, 2023Publication date: September 26, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Samuel Naffziger, William George En, John Wuu
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Publication number: 20240319903Abstract: Duplicating memory content with chipset attached memory is described. In accordance with the described techniques, contents of a system memory are duplicated on a chipset attached memory over a chipset link. Memory requests are serviced using the contents of the system memory and the contents on the chipset attached memory. Servicing the memory requests includes servicing a first portion of a read request using the contents of the system memory and a second, remaining portion of the read request using the contents on the chipset attached memory. Servicing the memory requests further includes communicating a write request to the system memory and to the chipset attached memory.Type: ApplicationFiled: March 22, 2023Publication date: September 26, 2024Applicant: Advanced Micro Devices, Inc.Inventors: William Robert Alverson, Jerry Anton Ahrens, Anil Harwani, Joshua Taylor Knight, Grant Evan Ley, Amitabh Mehra
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Publication number: 20240321668Abstract: A method for die pair partitioning can include providing a first circuit die having a first metal stack. The method can additionally include positioning a second circuit die having a second metal stack in a manner that places a temperature sensor in a transistor layer of the second circuit die in planar proximity to at least one hot spot located in an additional transistor layer of the first circuit die. The method can also include connecting the first metal stack of the first circuit die to the second metal stack of the second circuit die. Various other methods, systems, and computer-readable media are also disclosed.Type: ApplicationFiled: September 25, 2023Publication date: September 26, 2024Applicants: Advanced Micro Devices, Inc., Xilinx, Inc.Inventors: Thomas D. Burd, Gabriel H. Loh, John Wuu, Kevin Gillespie, Raja Swaminathan, Richard Schultz, Samuel Naffziger, Srividhya Venkataraman, Yan Wang
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Publication number: 20240321827Abstract: A method for circuit die stacking can include providing a first circuit die having a first metal stack, wherein the first circuit die corresponds to a primary thermal source of an integrated circuit including the first circuit die. The method can additionally include providing a second circuit die of the integrated circuit, wherein the second circuit die has a second metal stack and is configured for connection to at least one of a package substrate or an additional die. The method can also include connecting the first metal stack to the second metal stack. Various other methods, systems, and computer-readable media are also disclosed.Type: ApplicationFiled: September 25, 2023Publication date: September 26, 2024Applicants: Advanced Micro Devices, Inc., Xilinx, Inc.Inventors: Omar Zia, Thomas D Burd, Kevin Gillespie, Samuel Naffziger, Richard Schultz, Raja Swaminathan, Srividhya Venkataraman, Yan Wang, John Wuu
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Publication number: 20240319910Abstract: One or both of read and write accesses to a fabric-attached memory module via a fabric interconnect are monitored. In one or more implementations, offloading of one or more tasks accessing the fabric-attached memory module to a processor of a routing system associated with the fabric-attached memory module is initiated based on the read and write accesses to the fabric-attached memory module. Additionally or alternatively, replicating memory of the fabric-attached memory module to a cache memory of a computing node in the disaggregated memory system executing one or more tasks of a host application is initiated based on the write accesses to the fabric-attached memory module.Type: ApplicationFiled: May 31, 2024Publication date: September 26, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Vamsee Reddy Kommareddy, SeyedMohammad SeyedzadehDelcheh, Sergey Blagodurov
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Publication number: 20240321702Abstract: A method for providing backside power can include providing a first circuit die having a first metal stack. The method can also include connecting a second metal stack of a second circuit die to the first metal stack of the first circuit die, wherein a backside power delivery network is located in a passivation layer of at least one of the first circuit die or the second circuit die. Various other methods, systems, and computer-readable media are also disclosed.Type: ApplicationFiled: September 25, 2023Publication date: September 26, 2024Applicants: Advanced Micro Devices, Inc., Xilinx, Inc.Inventors: Yan Wang, Kevin Gillespie, Samuel Naffziger, Richard Schultz, Raja Swaminathan, Omar Zia, John Wuu
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Publication number: 20240321706Abstract: A method for implementing shared metal connectivity between 3D stacked circuit dies can include providing a first circuit die having a first metal stack. The method can additionally include providing a second circuit die having a second metal stack, wherein at least one metal layer of the second metal stack is utilized by both the first circuit die and the second circuit die. The method can also include connecting the second metal stack to the first metal stack of the first circuit die. Various other methods, systems, and computer-readable media are also disclosed.Type: ApplicationFiled: September 25, 2023Publication date: September 26, 2024Applicant: Advanced Micro Devices, Inc.Inventors: William George En, Samuel Naffziger, Regina T. Schmidt, Omar Zia, John Wuu
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Patent number: 12099723Abstract: A method for operating a memory having a plurality of banks accessible in parallel, each bank including a plurality of grains accessible in parallel is provided. The method includes: based on a memory access request that specifies a memory address, identifying a set that stores data for the memory access request, wherein the set is spread across multiple grains of the plurality of grains; and performing operations to satisfy the memory access request, using entries of the set stored across the multiple grains of the plurality of grains.Type: GrantFiled: September 29, 2022Date of Patent: September 24, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Jagadish B. Kotra, Marko Scrbak
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Patent number: 12099609Abstract: A computing system may implement a basic input/output system (BIOS) update method. The BIOS also includes identifying an installed central processing unit (CPU) of a computer system coupled to a BIOS chipset, selecting CPU firmware corresponding to the installed CPU from a plurality of CPU platform firmware stored on a first memory, and loading the CPU firmware into a shared portion of a second memory coupled to the BIOS chipset, where the shared portion of the second memory is configured to store the CPU firmware as secondary CPU firmware.Type: GrantFiled: December 18, 2020Date of Patent: September 24, 2024Assignee: Advanced Micro Devices, Inc.Inventor: Hsiu-Ming Chu
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Patent number: 12100660Abstract: A system and method for creating layout for standard cells are described. In various implementations, a semiconductor fabrication process (or process) forms a power signal route in a same metal zero track reserved for power rails. The process forms a contact layer with inserted spacing underneath the power signal route. Along the track, this contact layer has physical contact with the power signal route with a first distance greater than a width of any signal route in any metal layer orthogonal to the power signal route, and has no physical contact with the power signal route with a second distance greater than the width. One or more signal routes in the local interconnect layer are routed through this spacing. Without this spacing, signals would be routed through this area using the metal one layer, which increases signal congestion.Type: GrantFiled: October 4, 2021Date of Patent: September 24, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Partha Pratim Ghosh, Pratap Kumar Das, Prasanth M
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Patent number: 12099789Abstract: Methods, devices, and systems for information communication. Information transmitted from a host to a graphics processing unit (GPU) is received by information analysis circuitry of a field-programmable gate array (FPGA). A pattern in the information is determined by the information analysis circuitry. A predicted information pattern is determined, by the information analysis circuitry, based on the information. An indication of the predicted information pattern is transmitted to the host. Responsive to a signal from the host based on the predicted information pattern, the FPGA is reprogrammed to implement decompression circuitry based on the predicted information pattern. In some implementations, the information includes a plurality of packets. In some implementations, the predicted information pattern includes a pattern in a plurality of packets. In some implementations, the predicted information pattern includes a zero data pattern.Type: GrantFiled: December 10, 2020Date of Patent: September 24, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Kevin Y. Cheng, Sooraj Puthoor, Onur Kayiran
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Patent number: 12099091Abstract: A system and method for efficiently routing scan data between two dies used in three-dimensional packaging are described. In various implementations, a computing system includes at least a first semiconductor die (or first die) and a second die connected to one another within a three-dimensional (3D) package. The first die and the second die have multiple non-scan input/output (I/O) data channels between them for data transfer. The non-scan I/O data channels are partitioned into groups. The first die receives a given scan input data bit for testing a device under test (DUT) on the second die. The first die selects a first group of non-scan I/O data channels, and sends, to the second die, a copy of the given scan input data bit on each non-scan I/O data channel of the first group. The second die uses a voter circuit to determine the value of the given scan input data bit.Type: GrantFiled: July 15, 2022Date of Patent: September 24, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Songgan Zang, Qi Shao, Lifeng Zhang, Ahmet Tokuz, Lu Lu
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Patent number: 12101135Abstract: An integrated circuit includes a first terminal for receiving a data signal, a second terminal for receiving an external reference voltage, a receiver, and a reference voltage generation circuit. The receiver is powered by a power supply voltage with respect to ground and has a first input coupled to the first terminal, a second input for receiving a shared reference voltage, and an output for providing a data input signal. The reference voltage generation circuit is coupled to the second terminal and receives the power supply voltage. The reference voltage generation circuit is operable to form the shared reference voltage by mixing noise from the power supply voltage and noise from the second terminal.Type: GrantFiled: September 7, 2023Date of Patent: September 24, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Ramon Mangaser, Karthik Gopalakrishnan, Andy Huei Chu, Pradeep Jayaraman
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Patent number: 12099451Abstract: Systems and methods for cache replacement are disclosed. Techniques are described that determine a re-reference interval prediction (RRIP) value of respective data blocks in a cache, where an RRIP value represents a likelihood that a respective data block will be re-used within a time interval. Upon an access, by a processor, to a data segment in a memory, if the data segment is not stored in the cache, a data block in the cache to be replaced by the data segment is selected, utilizing a binary tree that tracks recency of data blocks in the cache.Type: GrantFiled: September 29, 2021Date of Patent: September 24, 2024Assignee: Advanced Micro Devices, Inc.Inventor: Paul J. Moyer
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Patent number: 12099867Abstract: Systems, apparatuses, and methods for implementing a multi-kernel wavefront scheduler are disclosed. A system includes at least a parallel processor coupled to one or more memories, wherein the parallel processor includes a command processor and a plurality of compute units. The command processor launches multiple kernels for execution on the compute units. Each compute unit includes a multi-level scheduler for scheduling wavefronts from multiple kernels for execution on its execution units. A first level scheduler creates scheduling groups by grouping together wavefronts based on the priority of their kernels. Accordingly, wavefronts from kernels with the same priority are grouped together in the same scheduling group by the first level scheduler. Next, the first level scheduler selects, from a plurality of scheduling groups, the highest priority scheduling group for execution. Then, a second level scheduler schedules wavefronts for execution from the scheduling group selected by the first level scheduler.Type: GrantFiled: May 30, 2018Date of Patent: September 24, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Sooraj Puthoor, Joseph Gross, Xulong Tang, Bradford Michael Beckmann
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Publication number: 20240311182Abstract: A device includes a communication scheduler to generate schedule trees for scheduling data communication among a plurality of nodes configured to perform a collective operation using data contributed from the plurality of nodes. The device includes data reduction logic to: identify one or more skewed nodes among the plurality of nodes, perform, according to a first set of schedule trees, a first operation to generate partial results based on data contributed from non-skewed nodes, and perform, according to a second set of schedule trees, a second operation to generate final results based on the partial results and data contributed from the one or more skewed nodes.Type: ApplicationFiled: March 17, 2023Publication date: September 19, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Kishore Punniyamurthy, Sagnik Basu, Khaled Hamidouche, Brandon Keith Potter
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Patent number: 12093181Abstract: A technique for operating a cache is disclosed. The technique includes based on a workload change, identifying a first allocation permissions policy; operating the cache according to the first allocation permissions policy; based on set sampling, identifying a second allocation permissions policy; and operating the cache according to the second allocation permissions policy.Type: GrantFiled: June 28, 2022Date of Patent: September 17, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Chintan S. Patel, Alexander J. Branover, Benjamin Tsien, Edgar Munoz, Vydhyanathan Kalyanasundharam