Abstract: The present invention provides embodiments of an apparatus that includes a pad configurable for connection to a voltage source that provides a first voltage and a buffer connected to the pad. The buffer includes a plurality of transistors that have nominal breakdown voltages that are less than the first voltage. The buffer is configured to maintain voltage differentials on the plurality of transistors that are less than the break-down voltage of the plurality of transistors during pull-down of a pad voltage from the first voltage to a selected low voltage level or during pull-up of the pad voltage from the selected low voltage level to the first voltage.

Abstract: Various methods, computer-readable mediums, articles of manufacture and systems are disclosed. In one aspect, a method is provided that includes generating a packet with a first semiconductor chip. The packet is destined to transit a first substrate and be received by a node of a second semiconductor chip. The packet includes a packet header and packet body. The packet header includes an identification of a first exit point from the first substrate and an identification of the node. The packet is sent to the first substrate and eventually to the node of the second semiconductor chip.

Abstract: In SOI devices, the PN junction of circuit elements, such as substrate diodes, is formed in the substrate material on the basis of the buried insulating material that provides increased etch resistivity during wet chemical cleaning and etch processes. Consequently, undue exposure of the PN junction formed in the vicinity of the sidewalls of the buried insulating material may be avoided, which may cause reliability concerns in conventional SOI devices comprising a silicon dioxide material as the buried insulating layer.

Abstract: An apparatus is disclosed for performing cache prefetching from non-uniform memories. The apparatus includes a processor configured to access multiple system memories with different respective performance characteristics. Each memory stores a respective subset of system memory data. The apparatus includes caching logic configured to determine a portion of the system memory to prefetch into the data cache. The caching logic determines the portion to prefetch based on one or more of the respective performance characteristics of the system memory that stores the portion of data.

Abstract: A semiconductor memory cell is provided that includes a trench capacitor and an access transistor. The access transistor comprises a source region, a drain region, a gate structure overlying the trench capacitor, and an active body region that couples the drain region to the source region. The active body region directly contacts the trench capacitor.

Abstract: A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench.

Abstract: A method for displaying two different content items on a main display device and a remote device includes displaying content in a first display mode, generating a content switch event to switch from the first display mode to a second display mode, and displaying content in the second display mode. In the first display mode, a first content item is displayed on the main display device. In the second display mode, a second content item is displayed on the main display device, and the first content item is displayed on the remote device.

Abstract: A system and method are disclosed wherein a processor of a plurality of processors coupled to shared memory, is configured to initiate execution of a section of code according to a first transactional mode of the processor. The processor is configured to execute a plurality of protected memory access operations to the shared memory within the section of code as a single atomic transaction with respect to the plurality of processors. The processor is further configured to initiate, within the section of code, execution of a subsection of the section of code according to a second transactional mode of the processor, wherein the first and second transactional modes are each associated with respective recovery actions that the processor is configured to perform in response to detecting an abort condition.

Abstract: Described is a data switching device comprising a plurality of input ports, a plurality of output ports, a plurality of first conductive connectors, a plurality of second conductive connectors, a plurality of crosspoint regions, and a memory device at each crosspoint region. The first conductive connectors are in communication with the input ports. The second conductive connectors are in communication with the output ports. Each crosspoint region includes a first conductive connector and a second conductive connector. The memory device is coupled between the first conductive connector and the second conductive connector for exchanging data between the input ports and the output ports.

Abstract: Described is an aggregation device comprising a plurality of virtual network interface cards (vNICs) and an input/output (I/O) processing complex. The vNICs are in communication with a plurality of processing devices. Each processing device has at least one virtual machine (VM). The I/O processing complex is between the vNICs and at least one physical NIC. The I/O processing complex includes at least one proxy NIC and a virtual switch. The virtual switch exchanges data with a processing device of the plurality of processing devices via a communication path established by a vNIC of the plurality of vNICs between the at least one VM and at least one proxy NIC.

Abstract: Integrated circuit packages comprise vias, each of which extends from a pad in communication with an integrated circuit on a semiconductor chip through insulating material overlying the semiconductor chip to an attachment surface facing a substrate. The portion of each via proximate the attachment surface is laterally offset from the portion proximate the pad from which it extends in a direction away from the centre of the semiconductor chip. Metallic material received in the vias mechanically and electrically interconnects the semiconductor chip to the substrate.

Abstract: The disclosed embodiments relate to apparatus for accurately, efficiently and quickly executing a multiplication instruction. The disclosed embodiments can provide a multiplier module having an optimized layout that can help speed up computation of a result during a multiply operation so that cycle delay can be reduced and so that power consumption can be reduced.

Abstract: A bus protocol compatible requester includes a bus protocol port for transmitting bus protocol compatible requests to a bus protocol link, and an extended atomic operation generation system, coupled to the bus protocol port, for generating an extended atomic operation by using at least one bit in a field of a standard bus protocol request other than an opcode field, and providing the extended atomic operation to the bus protocol port for transmission to a completer. A bus protocol compatible completer includes a bus protocol port for receiving bus protocol compatible requests from a bus protocol link, and an extended atomic operation execution system, coupled to the bus protocol port, for decoding an extended atomic operation according to at least one bit in a field of a standard bus protocol request other than an opcode field, and executing the extended atomic operation according to the at least one bit.

Abstract: An electronics chassis has many removable boards on sleds that are interconnected by a honeycomb interconnect structure. Interconnect boards in Y-planes and Z-planes are orthogonal to each other and form cells. Cooling air flows through the cells in an X direction, parallel to surfaces of the interconnect boards. The removable boards have connectors that mate with an edge of Z-divider interconnect boards. Fans blow air through the cells in the honeycomb structure unimpeded since no boards are perpendicular to the airflow. Notches in the rear of the Z-divider boards provide airflow equalization allowing closer spacing of fans to the honeycomb structure. A sled carrier honeycomb structure is placed in front of the honeycomb interconnect structure to guide sleds into position. Sled carrier dividers are offset from the Z-divider boards to allow removable boards to align with Z-divider boards in the Z-planes, parallel to airflow.

Abstract: An integrated circuit includes a register including a field for defining a high reliability mode of the integrated circuit and a cache and memory controller coupled to the register and responsive to the high reliability mode to access a memory to store, in a row of the memory, a first multiple number of cache lines, a first multiple number of tags corresponding to the first multiple number of cache lines, and reliability data corresponding to at least the first multiple number of cache lines.

Abstract: A method, apparatus and a system, for performing a process control using analysis of an upstream process is provided. The method comprises performing a first process on a workpiece and performing a qualitative analysis upon the workpiece relating to the first process, the qualitative analysis comprises analyzing at least one metrology measurement relating to the first process and a workpiece feature to evaluate a characteristic of the workpiece. The method further comprises selecting a process control parameter for performing a second process upon the workpiece based upon the qualitative analysis.

Abstract: A processing system is provided. The processing system includes a first processing unit coupled to a first memory and a second processing unit coupled to a second memory. The second memory comprises a coherent memory and a private memory that is private to the second processing unit.

Abstract: Described are aggregation devices and methods for interconnecting server nodes. The aggregation device can include an input region, an output region, and a memory switch. The input region includes a plurality of input ports. The memory switch has a shared through silicon via (TSV) memory coupled to the input ports for temporarily storing data received at the input ports from a plurality of source devices. The output region includes a plurality of output ports coupled to the TSV memory. The output ports provide the data to a plurality of destination devices. A memory allocation system coordinates a transfer of the data from the source devices to the TSV memory. The output ports receive and process the data from the TSV memory independently of a communication from the input ports.

Abstract: A contactless connector requires no physical contact. A terminated transmitting transmission line on a first board is parallel to a dual-terminated receiving transmission line on a second board. The boards are placed face-to-face with a small air gap in-between. A driver drives a driven pulse onto a first end of the transmitting transmission line. The driven pulse capacitively induces a positive induced pulse on the first end of the receiving transmission line. As the driven pulse travels from the first end to the second end of the transmitting transmission line, energy is transferred to the induced pulse, which travels down the receiving transmission line. Inductive coupling becomes stronger than capacitive as the length increases, so that at the second end, the induced pulse is negative and then swings positive. A Schmitt trigger receiver on the second end of the receiving transmission line detects the signal.

Abstract: A system and method are disclosed for allowing protection of larger areas than memory lines by monitoring accessed and dirty bits in page tables. More specifically, in some embodiments, a second associative structure with a different granularity is provided to filter out a large percentage of false positives. By providing the associative structure with sufficient size, the structure exactly specifies a region in which conflicting cache lines lie. If entries within this region are evicted from the structure, enabling the tracking for the entire index filters out a substantial number of false positives (depending on a granularity and a number of indices present). In some embodiments, this associative structure is similar to a translation look aside buffer (TLB) with 4 k, 2M entries.