Abstract: Various circuit boards and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling an electrically non-functional component to a surface of a first circuit board. The electrically non-functional component has a first elevation. The surface of the circuit board is adapted to have a semiconductor chip mounted thereon. An electrically functional component is mounted to the surface inward from the electrically non-functional component. The electrically functional component has a second elevation less than the first elevation.
Type:
Grant
Filed:
December 9, 2011
Date of Patent:
October 22, 2013
Assignees:
Advanced Micro Devices, Inc., ATI Technologies ULC
Inventors:
Neil R. McLellan, Liane Martinez, Yip Seng Low, Suming Hu
Abstract: A circuit includes a complementary current mode logic driver circuit and a dual feedback current mode logic bias circuit. The complementary current mode logic driver circuit provides a first output voltage and a second output voltage. The dual feedback current mode logic bias circuit includes a first feedback circuit and a second feedback circuit. The first feedback circuit provides a first bias voltage for the complementary current mode logic driver circuit in response to the first output voltage. The second feedback circuit provides a second bias voltage in response to the second output voltage.
Type:
Grant
Filed:
December 17, 2009
Date of Patent:
October 22, 2013
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Kevin Yikai Liang, Xin Liu, Arvind Bomdica, Ming-Ju Edward Lee
Abstract: A method is provided for selecting at least one of a plurality of slew rate control settings based at least upon a speed of data transmission and receiving input data where the input data is received at the data transmission speed. The method also includes switching the received input data in accordance with the selected at least one of a plurality of slew rate control settings and sending output data at the data transmission speed. Also provided is data driver device that includes at least one activation portion comprising one or more slew rate controls, a voltage-mode driver portion and at least a first current-mode driver portion. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create the data driver device. Also provided is a system including the data driver device, a data storage device and a processor device.
Type:
Grant
Filed:
May 24, 2011
Date of Patent:
October 22, 2013
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Xin Liu, Arvind Bomdica, Ming-Ju Edward Lee
Abstract: In a system having a plurality of processing nodes, a control node divides a task into a plurality of sub-tasks, and assigns the sub-tasks to one or more additional processing nodes which execute the assigned sub-tasks and return the results to the control node, thereby enabling a plurality of processing nodes to efficiently and quickly perform memory initialization and test of all assigned sub-tasks.
Abstract: A power controller can set the power state of a processor bridge based on which processor modules are in a communicative state. In addition, for a power state where selected processor modules are expected to be non-communicative, the power controller can set the supplied voltage to have a reduced voltage guard band as compared to other power states. These power management techniques can reduce the power consumed by the processor.
Type:
Application
Filed:
April 13, 2012
Publication date:
October 17, 2013
Applicants:
ATI TECHNOLOGIES ULC, ADVANCED MICRO DEVICES, INC.
Inventors:
Maurice B. Steinman, Alexander J. Branover, Denis J. Foley, Ljubisa Bajic
Abstract: The present invention provides a method and apparatus for handling lane-crossing instructions in an execution pipeline. One embodiment of the method includes conveying bits of an instruction from a register to an execution stage in a pipeline along a first data path that includes a lane crossing stage configured to change a first mapping of the register to the execution stage to a second mapping. The method also includes concurrently conveying the bits along a second data path from the register to the execution stage that bypasses the lane crossing stage. The method further includes selecting the first or second data path to provide the bits to the execution stage.
Abstract: A Scalable and Unified Compute System performs scalable, repairable general purpose and graphics shading operations, memory load/store operations and texture filtering. A Scalable and Unified Compute. Unit Module comprises a shader pipe array, a texture mapping unit, and a level one texture cache system. It accepts ALU instructions, input/output instructions, and texture or memory requests for a specified set of pixels, vertices, primitives, surfaces, or general compute work items from a shader program and performs associated operations to compute the programmed output data. The texture mapping unit accepts source data addresses and instruction constants in order to fetch, format, and perform instructed filtering interpolations to generate formatted results based on the specific corresponding data stored in a level one texture cache system. The texture mapping unit consists of an address generating system, a pre-formatter module, interpolator module, accumulator module and a format module.
Type:
Grant
Filed:
June 1, 2009
Date of Patent:
October 15, 2013
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Michael J. Mantor, Jeffrey T. Brady, Mark C. Fowler, Marcos P. Zini
Abstract: Various apparatus and methods of testing a semiconductor chip for soft defects are disclosed. In one aspect, a method of testing a semiconductor chip that has a surface and plural circuit structures positioned beneath the surface is provided. An irradiation mask directs light or heat to a series of fractional portions of the surface to perturb portions of the plural circuit structures. The irradiation mask is adjustable such that at least one of the exposed series of fractional portions is smaller than another of the series of fractional portions. The semiconductor chip undergoes a test pattern during the irradiation to each of the fractional portions to determine if a soft defect exists in any of the series of fractional portions. Multiple paths can be tested simultaneously to inform subsequent individual CTP path tests.
Type:
Grant
Filed:
February 14, 2011
Date of Patent:
October 15, 2013
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Abdullah M. Yassine, Rama Rao Goruganthu, Shannon B. Smith
Abstract: In one embodiment, a processor comprises one or more registers coupled to an execution core. The registers are configured to store an intercept configuration that identifies which of a plurality of intercept events are enabled for intercept during guest execution. Additionally, the intercept configuration identifies, for each enabled intercept event, which of at least two exit mechanisms are to be used in response to detection of the enabled intercept event. The execution core is configured to detect one of the enabled intercept events during execution of a guest and to exit the guest using the exit mechanism identified in the intercept configuration for that detected, enabled intercept event.
Type:
Grant
Filed:
April 26, 2007
Date of Patent:
October 15, 2013
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Benjamin C. Serebrin, Michael J. Haertel
Abstract: A power gate includes a series of electrical contacts along at least a portion of an integrated circuit and a series of power gate transistors electrically coupled to the electrical contacts on the integrated circuit to form a power gate boundary, e.g., at the integrated circuit periphery. The electrical contacts along at least a portion of a running length of the power gate boundary define a substantially non-linear profile. The non-linear profile provides increased contact density which improves current balancing across the electrical contacts and current throughput through the power gate. The non-linear profile is a sinusoidal or zigzag pattern with intermediate offset bump contacts. The contact profiles along the power gate boundary can include both linear and non-linear profiles.
Abstract: In a personal Internet communication device, a security key is stored on the master boot record. Any bootable device attempting to write operating system files or software files must have an authorized signature key in order to be eligible to install files on the personal Internet communication device.
Abstract: A device identifies array accesses of variables in a program code that includes multiple arrays, and identifies array access patterns for one of the array accesses. The device also determines an order of the array access patterns identified for the array accesses, and calculates, based on the order, distances between the array access patterns. The device further shares address calculations amongst the array accesses associated with array access patterns with one or more of the distances that are equivalent.
Abstract: A decision feedback equalization (DFE) receiver and method are provided. The DFE receiver is configured to sample data bits from a data bus. The DFE receiver includes a data sampler configured to sample a current data bit from the data bus using one of a first, second and third voltage reference. The DFE receiver also includes multiplexing logic configured to select one of the first, second and third voltage references based on a prior data bus level. The wherein the first voltage reference is selected if the prior data bus level was a logic zero. The second voltage reference is selected if the prior data bus level was a logic one. The third voltage reference is selected if the prior data bus level was tri-state.
Type:
Grant
Filed:
December 20, 2010
Date of Patent:
October 8, 2013
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Ramon Mangaser, Shefali Walia, Edoardo Prete, Jonathan P. Dowling, Gerald R. Talbot, Sharad N. Vittal
Abstract: In a personal Internet communication device, a system for directing the storage of files uses a file navigation program to control the location of where files may be stored by the user. With the system, attempts to save files by the file navigation program are directed to a predefined or default storage location in a fixed directory structure. All other applications on the person Internet communicator may also be modified to control file save operations. The person Internet communicator is further configured to maintain the file save associations with the predefined or default storage location, even when the user has previously saved files to another location.
Abstract: Existing multiprocessor computing systems often have insufficient memory coherency and, consequently, are unable to efficiently utilize separate memory systems. Specifically, a CPU cannot effectively write to a block of memory and then have a GPU access that memory unless there is explicit synchronization. In addition, because the GPU is forced to statically split memory locations between itself and the CPU, existing multiprocessor computing systems are unable to efficiently utilize the separate memory systems. Embodiments described herein overcome these deficiencies by receiving a notification within the GPU that the CPU has finished processing data that is stored in coherent memory, and invalidating data in the CPU caches that the GPU has finished processing from the coherent memory. Embodiments described herein also include dynamically partitioning a GPU memory into coherent memory and local memory through use of a probe filter.
Type:
Application
Filed:
August 31, 2012
Publication date:
October 3, 2013
Applicants:
ATI Technologies ULC, Advanced Micro Devices, Inc.
Inventors:
Anthony ASARO, Kevin NORMOYLE, Mark HUMMEL
Abstract: Embodiments of the present invention provides for the execution of threads and/or workitems on multiple processors of a heterogeneous computing system in a manner that they can share data correctly and efficiently. Disclosed method, system, and article of manufacture embodiments include, responsive to an instruction from a sequence of instructions of a work-item, determining an ordering of visibility to other work-items of one or more other data items in relation to a particular data item, and performing at least one cache operation upon at least one of the particular data item or the other data items present in any one or more cache memories in accordance with the determined ordering. The semantics of the instruction includes a memory operation upon the particular data item.
Type:
Application
Filed:
March 30, 2012
Publication date:
October 3, 2013
Applicants:
ATI Technologies ULC, Advanced Micro Devices, Inc.
Inventors:
Anthony ASARO, Kevin Normoyle, Mark Hummel, Norman Rubin, Mark Fowler
Abstract: The present system enables receiving a request from an I/O device to translate a virtual address to a physical address to access the page in system memory. One or more memory attributes of the page defining a cacheability characteristic of the page is identified. A response including the physical address and the cacheability characteristic of the page is sent to the I/O device.
Type:
Application
Filed:
March 30, 2012
Publication date:
October 3, 2013
Applicants:
ATI Technologies ULC, Advanced Micro Devices, Inc.
Inventors:
Andrew KEGEL, Mark Hummel, Anthony Asaro
Abstract: A method, performed by a processor, of determining a square root using a single processor cycle per iteration is described. The method includes, in a single cycle: obtaining, from a stored lookup table, a quotient digit and a square of the quotient digit; retrieving a current solution; and determining a new solution using the current solution and the quotient digit. Circuitry configured to perform the method is described.
Type:
Application
Filed:
March 30, 2012
Publication date:
October 3, 2013
Applicant:
ADVANCED MICRO DEVICES, INC.
Inventors:
Carl E. Lemonds, Jay E. Fleischman, David M. Russinoff
Abstract: Embodiments described herein include a system, a computer-readable medium and a computer-implemented method for processing a system call (SYSCALL) request. The SYSCALL request from an invisible processing device is stored in a queueing mechanism that is accessible to a visible processing device, where the visible processing device is visible to an operating system and the invisible processing device is invisible to the operating system. The SYSCALL request is processed using the visible processing device, and the invisible processing device is notified using a notification mechanism that the SYSCALL request was processed.
Type:
Application
Filed:
March 29, 2013
Publication date:
October 3, 2013
Applicant:
Advanced Micro Devices, Inc.
Inventors:
Benjamin Thomas Sander, Michael Clair Houston, Keith Lowery, Newton Cheung
Abstract: Embodiments of the present invention provide a method of a first processor using a memory resource associated with a second processor. The method includes receiving a memory instruction from a first processor process, wherein the memory instruction refers to a shared memory address (SMA) that maps to a second processor memory. The method also includes mapping the SMA to the second processor memory, wherein the mapping produces a mapping result and providing the mapping result to the first processor.
Type:
Application
Filed:
August 17, 2012
Publication date:
October 3, 2013
Applicants:
Advanced Micro Devices, Inc., ATI Technologies ULC
Inventors:
Anthony Asaro, Kevin Normoyle, Mark Hummel