Abstract: A method and apparatus generates thermal partitions for metal interconnects of an integrated circuit, based on interconnect self heat data and mutual heat data. Each of the thermal partitions includes data identifying thermally related interconnects and respective temperature values associated with each of the thermally related interconnects. Thermally related partitions that can be computed efficiently and simultaneously and the results then integrated using superposition for the full chips.

Abstract: A video processing apparatus and methodology are implemented as a combination of a processor and a video decoding hardware block to decode video data by performing piecewise processing of overlap smoothing and in-loop deblocking in a macroblock-based fashion. With this approach, a smaller on-board memory may be used for the in-loop filtering operations of the video decoding hardware block. By pipelining the piecewise processing operations, latency in the filtering operations is hidden and the filtering output is smoothed, thereby avoiding the need for bursts of fetching and storing of blocks.

Abstract: Disclosed are methods and systems for granting an application-specific integrated circuit (ASIC) in a multi-ASIC environment controlled access to a shared resource. A system includes a first ASIC, a second ASIC, and a shared memory that stores a shared resource and a data set partitioned into fields. The first ASIC writes data to a first subset of the fields and reads data from the fields. The first ASIC includes first logic that computes a first value based on the data read from the fields. The second ASIC writes data to a second subset of the fields and reads data from the fields. The second ASIC includes second logic that computes a second value based on the data read from the fields. Based on the first and second values respectively computed by the first and second logic, only one of the first and second ASICs gains access to the shared resource.

Abstract: A method of manufacturing is provided that includes providing a semiconductor chip device that has a circuit board and a first semiconductor chip coupled thereto. A lid is placed on the circuit board. The lid includes an opening and an internal cavity. A liquid thermal interface material is placed in the internal cavity for thermal contact with the first semiconductor chip and the circuit board.

Abstract: A loop predictor and a method for instruction fetching using a loop predictor. A processor may include a loop predictor in addition to a primary branch predictor. A relatively common scenario in program execution is that a set of branches repeat over and over forming a loop. The loop may be detected based on a repeated pattern of access to a data structure used for branch prediction. Once a loop is detected and it may be determined whether the codes would stay in the loop for at least a duration sufficient to disable the branch prediction. On a determination that the detected loop is locked, a sequence of instruction addresses in one iteration of the detected loop may be captured in a buffer and the branch predictor may be turned off and a sequence of fetch instructions may be played from the buffer.

Abstract: A method and apparatus for determining a temperature of a semiconductor device is provided herein. One aspect of the disclosed subject matter is seen in a temperature sensing device. The temperature sensing device comprises a diode and a circuit. The diode is adapted to be reverse biased by a charging voltage applied thereto. The circuit determines a temperature of the diode based on a rate that the voltage on the diode discharges in response to the charging voltage being uncoupled from the diode.

Abstract: By moderately introducing defects into a highly conductive material, such as copper, the resistance versus temperature behavior may be significantly modified so that enhanced electromigration behavior and/or electrical performance may be obtained in metallization structures of advanced semiconductor devices. The defect-related portion of the resistance may be moderately increased so as to change the slope of the resistance versus temperature curve, thereby allowing the incorporation of impurity atoms for enhancing the electromigration endurance while not unduly increasing the overall resistance at the operating temperature or even reducing the corresponding resistance at the specified operating temperature. Thus, by appropriately designing the electrical resistance for a target operating temperature, both the electromigration behavior and the electrical performance may be enhanced.

Abstract: In a CPU, the CPU having multiple CPU cores, each core having a first machine specific register, a second machine specific register, and microcode which when executed causes a write notification to be issued to the physical address contained in the second machine specific register; receiving in the first machine specific register of a CPU core, a physical page table/page directory base address, receiving in the second machine specific register of the CPU core, a physical address pointing to a location controlled by the IOMMUv2, determining that a control register of the CPU core has been updated, and responsive to the determination that the control register has been updated, executing microcode in the CPU core that causes a write notification to be issued to the physical address contained in the second machine specific register, wherein the physical address is able to receive writes that affect IOMMUv2 page table invalidations.

Abstract: A first plurality of clock signals including a first clock signal and a second clock signal is received, the first and second clock signal out of phase with each other. A second plurality of clock signals comprising a third clock signal and a fourth clock signal is received, the third and fourth clock signals out of phase with each other. A plurality of enable signals are received. A fifth clock signal is determined based on the first plurality of clock signals and the plurality of enable signals. A sixth clock signal is determined based on the second plurality of clock signals and the plurality of enable signals. A seventh clock signal is determined based on the fifth clock signal and the sixth clock signal.

Abstract: The described embodiments include a processor that handles operations during transactions. In these embodiments, the processor comprises one or more cores. During operation, at least one core is configured to monitor the acquisition of time stamps during transactions. The at least one core is further configured to prevent the acquisition of time stamps that meet predetermined conditions.

Abstract: A method and circuitry for calibrating the gain of a VCO (voltage controlled oscillator) is disclosed. In one embodiment, a circuit includes a comparator configured to provide a first indication if the VCO gain is not within the specified gain range, and a second indication if the VCO is within the specified gain range. The circuit further includes a control unit configured to, upon occurrence of at least a first cycle of a clock signal, cause adjustment of the VCO gain responsive to receiving the first indication. For each one or more successive cycles of the clock signal, the control unit is configured to cause corresponding adjustments of the VCO gain until the comparator provides the second indication. The control unit is configured to discontinue adjustments to the VCO gain responsive to receiving the second indication.

Abstract: Electronic component protection power supply clamp circuits comprising a plurality of p-type channel metal-oxide-semiconductor (PMOS) and n-type channel metal-oxide-semiconductor (NMOS) transistors are described. These clamp circuits use a feedback latching circuit to retain an electrostatic discharge (ESD)-triggered state and efficiently conduct ESD current that has been diverted into the power supply, in order to dissipate ESD energy. The feedback latching circuit also maintains a clamp transistor in its off state if the clamp circuit powers up untriggered, thus enhancing the clamp circuit's immunity to noise during normal operation. Passive resistance initialization of key nodes to an untriggered state, as well as passive resistance gate input loading of a large ESD clamping transistor, further enhances the clamp circuit's immunity to false triggering.

Abstract: An integrated circuit is capable of controlling a communication signal by using power ramp controlled communication buffer logic to generate an outgoing communication signal based on a detected voltage on a voltage source. The voltage source is necessary to supply power for power ramp controlled communication buffer logic. The voltage on the voltage source may be detected using power ramp sensor logic. The outgoing communication signal is based on a core logic output signal if the detected voltage is greater than or equal to a predetermined voltage level. If, the detected voltage is less than the predetermined voltage level, the outgoing communication signal is predetermined to be one of: a tristate outgoing communication signal, a logic one outgoing communication signal and a logic zero outgoing communication signal. Power ramp controlled communication buffer logic may also generate a core logic input signal based on an incoming communication signal in response to the detected voltage.

Abstract: Content-Addressable Memory (CAM) arrays and related circuitry for integrated circuits and CAM array comparison methods are provided such that relatively low power is used in the operation of the CAM circuitry. A binary value pair is stored in a pair of CAM memory elements. A comparison signal is provided to comparator circuitry that uniquely represents the stored binary values. A match signal is input to the comparator circuitry that uniquely represents a binary value pair to be compared with the stored binary value pair. In one example, a transistor is operated to output a positive match result signal only on a condition that the comparison signal provided to the comparator circuitry and match signal input to the comparator circuitry represent the same binary value pair. In that example, no transistor of the comparator circuitry is operated when the comparison signal provided to the comparator circuitry and match signal input to the comparator circuitry represent different binary value pairs.

Abstract: A technique for characterizing a communications interface includes determining a voltage margin and a timing margin of the interface based on data sampled by a sampling device of a receiver of the interface. In at least one embodiment of the invention, a method for determining margin associated with a receiver circuit of an integrated circuit includes periodically sampling a signal over a time period by a receiver sampling circuit of the receiver circuit to generate a sampled version of the signal. The method includes incrementally varying a value of the parameter associated with the signal. The varying of the parameter is through a range of values of the parameter over the time period. The method includes determining a margin value of the receiver circuit associated with the parameter based, at least in part, on the sampled version of the signal.

Abstract: Apparatus and methods for storing data in a block to provide improved accessibility of the stored data in two or more dimensions. The data is loaded into memory macros constituting a row of the block such that sequential values in the data are loaded into sequential memory macros. The data loaded in the row is circularly shifted a predetermined number of columns relative to the preceding row. The circularly shifted row of data is stored, and the process is repeated until a predetermined number of rows of data are stored. A two dimensional (2D) data block is thereby formed. Each memory macro is a predetermined number of bits wide and each column is one memory macro wide.

Abstract: A processor integrated circuit has one or more processor cores and a power management controller in a North-Bridge that generates a first power state recommendation for the one or more processor cores. The North-Bridge also receives a second power state recommendation from a South-Bridge integrated circuit. The North-Bridge determines a final power state for the one or more processor cores based on the first and second power state recommendations.

Abstract: A memory device includes a number of memory cells and a dielectric layer formed over the memory cells. The memory device also includes contacts formed in the dielectric layer and spacers formed adjacent the side surfaces of the contacts. The spacers may inhibit leakage currents from the contacts.

Abstract: A processor or an integrated circuit chip including a debug state machine (DSM) that allows for programming complex triggering sequences for flexible and efficient debug visibility is disclosed. The DSM centralizes control of local debug functions such as trace start and stop, trace filtering, cross triggering between DSMs, clock stopping, triggering a system debug mode interrupt, flexible microcode interface, and the like. The DSM is configured to receive triggers from a processor core, other DSMs, a northbridge, other sockets, and the like and initiate a programmed action on a condition that a corresponding trigger or a sequence of triggers occurs.

Abstract: Embodiments include implementing a phase detector for a delay-locked loop (DLL) circuit that is operable to detect substantially 270 degree and substantially 540 degree phase differences between two clock signals. In an embodiment, a DLL circuit comprises a delay line receiving a system clock signal and generating phase shifted clock signals, a phase detector receiving the system clock signal and phase shifted clock signal, and configured to generate corresponding up and down signals upon detection of a phase shift of substantially 270 degrees between the system clock signal and the phase shifted clock signal, a charge pump coupled to the phase detector, and configured to receive the up and down signals and generate a control signal responsive to thereto, and a regulator circuit to receive the control signal from the charge pump and generate a voltage control signal to the delay chain to control delay of the system clock signal.