Patents Assigned to Advanced Micro Device, Inc.
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Patent number: 12093124Abstract: A method for receiving a multi-level error signal having more than two logic levels includes oversampling the multi-level error signal to provide sampled symbols, wherein a first level of the multi-level error signal indicates no error, and second and third levels of the multi-level error signal indicate first and second error conditions, respectively. The sampled signals are de-serialized to provide sets of symbols. A start of a symbol period is determined in response to detecting that a given sample is different from a prior sample, and the prior sample indicates no error. The sets of symbols are filtered to provide corresponding output symbols based on the start.Type: GrantFiled: September 29, 2022Date of Patent: September 17, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Aaron D Willey, Karthik Gopalakrishnan, Pradeep Jayaraman, Ramon Mangaser
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Patent number: 12093689Abstract: A processing system that includes a shared data fabric resets a first client processor while operating a second client processor. The first client processor is instructed to stop making requests to one or more devices of the shared data fabric. Status communications are blocked between the first client processor and a memory controller, the second client processor, or both, such that the first client processor enters a temporary offline state. The first client processor is indicated as being non-coherent. Accordingly, when the processor is reset some errors and efficiency losses due messages sent during or prior to the reset are prevented.Type: GrantFiled: September 25, 2020Date of Patent: September 17, 2024Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Benjamin Tsien, Alexander J. Branover, John Petry, Chen-Ping Yang, Rostyslav Kyrychynskyi, Vydhyanathan Kalyanasundharam
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Publication number: 20240302879Abstract: Performance adaptation for an integrated circuit includes receiving, by a workload prediction system of a hardware processor, telemetry data for one or more systems of the hardware processor. A workload prediction is determined by processing the telemetry data through a workload prediction model executed by a workload prediction controller of the workload prediction system. A profile is selected, from a plurality of profiles, that matches the workload prediction. The selected profile specifies one or more operating parameters for the hardware processor. The selected profile is provided to a power management controller of the hardware processor for controlling an operational characteristic of the one or more systems.Type: ApplicationFiled: March 8, 2023Publication date: September 12, 2024Applicant: Advanced Micro Devices, Inc.Inventor: Julian Daniel John
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Patent number: 12086422Abstract: A framework disclosed herein extends a relaxed, scoped memory model to a system that includes nodes across a commodity network and maintains coherency across the system. A new scope, cluster scope, is defined, that allows for memory accesses at scopes less than cluster scope to operate on locally cached versions of remote data from across the commodity network without having to issue expensive network operations. Cluster scope operations generate network commands that are used to synchronize memory across the commodity network.Type: GrantFiled: May 19, 2023Date of Patent: September 10, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Michael W. LeBeane, Khaled Hamidouche, Hari S. Thangirala, Brandon Keith Potter
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Patent number: 12086009Abstract: Methods and systems are disclosed for transitioning, by a hardware-based controller, a system on a chip (SoC) into different power states. Techniques disclosed include tracking, by the controller, metrics associated with the SoC and transitioning, by the controller, the SoC from a first power state to a second power state based on the tracked metrics. Were the total amount of power that is used by at least a portion of the transition between the first power state to the second power state and a time spent in the second power state is less than the total amount of power that would have been used by remaining in the first power state.Type: GrantFiled: March 31, 2022Date of Patent: September 10, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Alexander J. Branover, Thomas J. Gibney, Mihir Shaileshbhai Doctor, Indrani Paul, Benjamin Tsien, Stephen V. Kosonocky, John P. Petry, Christopher T. Weaver
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Patent number: 12086418Abstract: A memory sprint controller, responsive to an indicator of an irregular memory access phase, causes a memory controller to enter a sprint mode in which it temporarily adjusts at least one timing parameter of a dynamic random access memory (DRAM) to reduce a time in which a designated number of activate (ACT) commands are allowed to be dispatched to the DRAM.Type: GrantFiled: March 31, 2023Date of Patent: September 10, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Vignesh Adhinarayanan, Michael Ignatowski, Hyung-Dong Lee
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Patent number: 12086899Abstract: Systems and methods related to run-time selection of a render mode in which to execute command buffers with a graphics processing unit (GPU) of a device based on performance data corresponding to the device are provided. A user mode driver (UMD) or kernel mode driver (KMD) executed at a central processing unit (CPU) selects abinning mode based on whether performance data that includes sensor data or performance counter data indicates that an associated binning condition or override condition has been met. The UMD or the KMD causes pending command buffers to be patched to execute in the selected binning mode based on whether the binning mode is enabled or disabled.Type: GrantFiled: September 25, 2020Date of Patent: September 10, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Anirudh R. Acharya, Ruijin Wu, Paul E. Ruggieri
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Patent number: 12086447Abstract: A processing system includes a first processor couplable to a first memory and a second memory. In response to a page migration trigger for a page in the first memory, the first processor is configured to, responsive to the page being a read-only page storing code for execution, initiate migration of the page to a code cache portion of a second memory associated with a second processor and shared by multiple processes executing at the second processor, and to configure each process of a set of processes executing at the second processor to access and execute the code from the code cache portion.Type: GrantFiled: December 18, 2019Date of Patent: September 10, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Khaled Hamidouche, Michael W. Lebeane, Hari S. Thangirala
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Publication number: 20240296128Abstract: An input/output memory management unit includes a control logic circuit and a device table entry valid bit array. The control logic circuit provides physical addresses in response to virtual addresses of memory access requests from a plurality of input/output devices. The device table entry valid bit array stores a plurality of valid bits corresponding to different ones of the plurality of input/output devices. The control logic circuit accesses a first valid bit corresponding to a first input/output device from the device table entry valid bit array, and selectively accesses a device table in a system memory in response to a state of the valid bit.Type: ApplicationFiled: March 2, 2023Publication date: September 5, 2024Applicant: Advanced Micro Devices, Inc.Inventor: Wei Sheng
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Publication number: 20240295898Abstract: Methods and systems are disclosed for clock delay compensation in a multiple chiplet system. Techniques disclosed include distributing, by a clock generator, a clock signal across distribution trees of respective chiplets; measuring phases, by phase detectors, where each phase measurement is associated with a chiplet of the chiplets and is indicative of a propagation speed of the clock signal through the distribution tree of the chiplet. Then, for each chiplet, techniques are further disclosed that determine, by a microcontroller, based on the phase measurements associated with the chiplet, a delay offset, and that delay, based on the delay offset, the propagation of the clock signal through the distribution tree of the chiplet using a delay unit associated with the chiplet.Type: ApplicationFiled: May 14, 2024Publication date: September 5, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Anwar Kashem, Craig Daniel Eaton, Pouya Najafi Ashtiani, Deepesh John
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Patent number: 12079145Abstract: A processor distributes memory timing parameters and data among different memory modules based upon memory access patterns. The memory access patterns indicate different types, or classes, of data for an executing workload, with each class associated with different memory access characteristics, such as different row buffer hit rate levels, different frequencies of access, different criticalities, and the like. The processor assigns each memory module to a data class and sets the memory timing parameters for each memory module according to the module's assigned data class, thereby tailoring the memory timing parameters for efficient access of the corresponding data.Type: GrantFiled: January 30, 2023Date of Patent: September 3, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Max Ruttenberg, Vendula Venkata Srikant Bharadwaj, Yasuko Eckert, Anthony Gutierrez, Mark H. Oskin
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Patent number: 12079634Abstract: A technique for processing qubits in a quantum computing device is provided. The technique includes determining that, in a first cycle, a first quantum processing region is to perform a first quantum operation that does not use a qubit that is stored in the first quantum processing region, identifying a second quantum processing region that is to perform a second quantum operation at a second cycle that is later than the first cycle, wherein the second quantum operation uses the qubit, determining that between the first cycle and the second cycle, no quantum operations are performed in the second quantum processing region, and moving the qubit from the first quantum processing region to the second quantum processing region.Type: GrantFiled: February 18, 2020Date of Patent: September 3, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Onur Kayiran, Jieming Yin, Yasuko Eckert
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Patent number: 12079919Abstract: Described herein is a technique for performing operations for a bounding volume hierarchy. The techniques include: for a bounding box with quantized orientation, the bounding box being part of a bounding volume hierarchy, rotating a ray according to the quantized orientation to generate a rotated ray; performing an intersection test against the bounding box with the rotated ray; and according to the results of the intersection test, continuing traversal of the bounding volume hierarchy.Type: GrantFiled: September 29, 2021Date of Patent: September 3, 2024Assignee: Advanced Micro Devices, Inc.Inventors: David Ronald Oldcorn, Matthäus G. Chajdas, Michael A. Kern
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Patent number: 12079490Abstract: Methods and systems are disclosed for frequency transitioning in a memory interface system. Techniques disclosed include receiving a signal indicative of a change in operating frequency, into a new frequency, in a processing unit interfacing with memory via the memory interface system; switching the system from a normal mode of operation into a transition mode of operation; updating control and state register (CSR) banks of respective transceivers of the system through a mission bus used during the normal mode of operation; and operating the system in the new frequency.Type: GrantFiled: December 29, 2021Date of Patent: September 3, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Anwar Kashem, Craig Daniel Eaton, Pouya Najafi Ashtiani
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Patent number: 12080632Abstract: Apparatuses, systems and methods for efficiently generating a package substrate. A semiconductor fabrication process (or process) fabricates each of a first glass package substrate and a second glass package substrate with a redistribution layer on a single side of a respective glass wafer. The process flips the second glass package substrate upside down and connects the glass wafers of the first and second glass package substrates together using a wafer bonding technique. In some implementations, the process uses copper-based wafer bonding. The resulting bonding between the two glass wafers contains no air gap, no underfill, and no solder bumps. Afterward, the side of the first glass package substrate opposite the glass wafer is connected to at least one integrated circuit. Additionally, the side of the second glass package substrate opposite the glass wafer is connected to a component on the motherboard through pads on the motherboard.Type: GrantFiled: September 29, 2021Date of Patent: September 3, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Deepak Vasant Kulkarni, Rahul Agarwal, Rajasekaran Swaminathan, Chintan Buch
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Patent number: 12080032Abstract: A processing unit, method, and medium for decompressing or generating textures within a graphics processing unit (GPU). The textures are compressed with a variable-rate compression scheme such as JPEG. The compressed textures are retrieved from system memory and transferred to local cache memory on the GPU without first being decompressed. A table is utilized by the cache to locate individual blocks within the compressed texture. A decompressing shader processor receives compressed blocks and then performs on-the-fly decompression of the blocks. The decompressed blocks are then processed as usual by a texture consuming shader processor of the GPU.Type: GrantFiled: June 21, 2021Date of Patent: September 3, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Konstantine Iourcha, John W. Brothers
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Publication number: 20240289276Abstract: A uniform cache for fast data access including a plurality of compute units (CUs) and a plurality of LO caches with an arrangement in a network configuration where each one of CUs is surrounded by a first group of the plurality of LO caches and each of the plurality of LO caches is surrounded by a LO cache group and CU group. One of CUs, upon a request for data, queries the surrounding first group of LO caches to satisfy the request. If the first group of LO caches fails to satisfy the data request, the first group of the plurality of LO caches queries a second group of adjacent LO caches to satisfy the request. If the second group of adjacent LO caches fails to satisfy the data request, the second group of adjacent LO caches propagating the query to the next group of LO caches.Type: ApplicationFiled: May 6, 2024Publication date: August 29, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Dazheng Wang, Xuwei Chen
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Publication number: 20240291371Abstract: The disclosed voltage regulator includes multiple voltage converter circuits. Each of the voltage converter circuits can be configured to operate at respective switching frequencies to deliver current to an output supply voltage. The voltage regulator can include a control circuit that regulates the output supply voltage using the voltage converter circuits. Various other methods and systems are also disclosed.Type: ApplicationFiled: September 12, 2023Publication date: August 29, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Justin Burkhart, Matt Straayer, Eric Bohannon
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Patent number: 12072754Abstract: A method and apparatus for managing a controller includes indicating, by a processor of a first device, to the controller of a second device to enter a second power state from a first power state. The controller of the second device responds to the processor of the first device with a confirmation. The processor of the first device transmits a signal to the controller of the second device to enter the second power state. Upon receiving a wake event, the controller of the second device exits the second device from the second power state to the first power state.Type: GrantFiled: September 24, 2021Date of Patent: August 27, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Alexander J. Branover, Christopher T. Weaver, Indrani Paul, Benjamin Tsien, Mihir Shaileshbhai Doctor, Stephen V. Kosonocky, John P. Petry, Thomas J. Gibney
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Patent number: 12073114Abstract: A memory controller includes a command queue with multiple entry stacks, each with a plurality of entries holding memory access commands, one or more parameter indicators each holding a respective characteristic common to the plurality of entries, and a head indicator designating a current entry for arbitration. An arbiter has a single command input for each entry stack. A command queue loader circuit receives incoming memory access commands and loads entries of respective entry stacks with memory access commands having the respective characteristic of each of the one or more parameter indicators in common.Type: GrantFiled: September 30, 2021Date of Patent: August 27, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Hideki Kanayama, Eric M. Scott