Patents Assigned to Advanced Micro Device, Inc.
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Patent number: 12026080Abstract: Systems and methods for building applications by automatically incorporating application performance data into the application build process are disclosed. By capturing build settings and performance data from prior applications being executed on different computing systems such as bare metal and virtualized cloud instances, a performance database may be maintained and used to predict build settings that improve application performance (e.g., on a specific computing system or computing system configuration).Type: GrantFiled: August 17, 2021Date of Patent: July 2, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Max Alt, Paulo Roberto Pereira de Souza filho
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Publication number: 20240211160Abstract: System memory training with chipset attached memory is described. In accordance with the described techniques, a request is received to train a system memory of a device. Responsive to the request, contents of the system memory are transferred to a chipset attached memory. The device is operated using the contents from the chipset attached memory. While the device is being operated using the contents from the chipset attached memory, the system memory is dynamically trained. After the training is complete, the contents are transferred back from the chipset attached memory to the trained system memory.Type: ApplicationFiled: December 27, 2022Publication date: June 27, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Jerry Anton Ahrens, William Robert Alverson, Joshua Taylor Knight, Amitabh Mehra, Anil Harwani, Grant Evan Ley
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Publication number: 20240212908Abstract: The disclosed inductor includes a magnetic material surrounding a conductive core. The magnetic material and conductive core can be embedded in a substrate. The magnetic material and conductive core can be formed in the substrate, using a magnetic composite material. Various other systems and methods are also disclosed.Type: ApplicationFiled: September 29, 2023Publication date: June 27, 2024Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Robert Grant Spurney, Alexander Helmut Pfeiffenberger, Sri Ranga Sai Boyapati, Deepak Vasant Kulkarni
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Publication number: 20240211134Abstract: A memory controller includes an arbiter, a vector arithmetic logic unit (VALU), a read buffer and a write buffer both coupled to the VALU, and an atomic memory operation scheduler. The VALU performs scattered atomic memory operations on arrays of data elements responsive to selected memory access commands. The atomic memory operation scheduler is for scheduling atomic memory operations at the VALU; identifying a plurality of scattered atomic memory operations with commutative and associative properties, the plurality of scattered atomic memory operations on at least one element of an array of data elements associated with an address; and commanding the VALU to perform the plurality of scattered atomic memory operations.Type: ApplicationFiled: December 23, 2022Publication date: June 27, 2024Applicant: Advanced Micro Devices, Inc.Inventors: John Kalamatianos, Karthik Ramu Sangaiah, Anthony Thomas Gutierrez
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Publication number: 20240211362Abstract: An exemplary system includes and/or represents an agent and a machine check architecture. In one example, the machine check architecture includes and/or represents at least one circuit configured to report errors via at least one reporting register. In this example, the machine check architecture also includes and/or represents at least one error-injection register configured to cause the circuit to inject at least one fabricated error report into the reporting register in response to a write operation performed by the agent on at least one bit of the error-injection register. Various other devices, systems, and methods are also disclosed.Type: ApplicationFiled: December 27, 2022Publication date: June 27, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Vilas Sridharan, Hanbing Liu, Francisco L. Duran
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Publication number: 20240211393Abstract: In accordance with the described techniques for leveraging processing in memory registers as victim buffers, a computing device includes a memory, a processing in memory component having registers for data storage, and a memory controller having a victim address table that includes at least one address of a row of the memory that is stored in the registers. The memory controller receives a request to access the row of the memory and accesses data of the row from the registers based on the address of the row being included in the victim address table.Type: ApplicationFiled: December 27, 2022Publication date: June 27, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Jagadish B Kotra, Dong Kai Wang
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Publication number: 20240212259Abstract: An implementation comprises traversing a bounding volume hierarchy for each ray of a plurality of rays concurrently using a plurality of execution items. In response to determining that a first execution item of the plurality of execution items is finished traversing the bounding volume hierarchy for a first ray of the plurality rays, the embodiment causes the first execution item to traverse the bounding volume hierarchy for a second ray of the plurality of rays while a second execution item of the plurality of execution items traverses the bounding volume hierarchy for the second ray. And the embodiment comprises initiating side-effects with the first and second execution items in an order indicated by the bounding volume hierarchy.Type: ApplicationFiled: December 27, 2022Publication date: June 27, 2024Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: David William John Pankratz, Daniel James Skinner, Michael John Livesley
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Publication number: 20240211402Abstract: In accordance with the described techniques for condensed coherence directory entries for processing in memory, a computing device includes a core that includes a cache, a memory that includes multiple banks, a coherence directory that includes a condensed entry indicating that data associated with a memory address and the multiple banks is not stored in the cache, and a cache coherence controller. The cache coherence controller receives a processing-in-memory command to the memory address and performs a single lookup in the coherence directory for the processing-in-memory command based on inclusion of the condensed entry in the coherence directory.Type: ApplicationFiled: December 27, 2022Publication date: June 27, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Travis Henry Boraten, Varun Agrawal, Michael Warren Boyer
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Publication number: 20240211416Abstract: Physical adjustment to system memory with chipset attached memory is described. In accordance with the described techniques, an indication for making one or more physical adjustments to system memory of a device is received. Contents of the system memory are transferred via a chipset link to a chipset attached memory. The device is operated using the contents from the chipset attached memory while the one or more physical adjustments are made to adjust the system memory. After the one or more physical adjustments, the contents are transferred back from the chipset attached memory to the adjusted system memory via the chipset link.Type: ApplicationFiled: December 27, 2022Publication date: June 27, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Jerry Anton Ahrens, William Robert Alverson, Joshua Taylor Knight, Amitabh Mehra, Anil Harwani, Grant Evan Ley
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Publication number: 20240211407Abstract: A memory request issue counter (MRIC) is maintained that is incremented for every memory access a central processing unit core makes. A region reuse distance table is also maintained that includes multiple entries each of which stores the region reuse distance for a corresponding region. When a memory access request for a physical address is received, a reuse distance for the physical address is calculated. This reuse distance is the difference between the current MRIC value and a previous MRIC value for the physical address. The previous MRIC value for the physical address is the MRIC value the MRIC had when a memory access request for the physical address was last received. A region reuse distance for a region that includes the physical address is generated based on the reuse distance for the physical address and used to manage the cache.Type: ApplicationFiled: December 27, 2022Publication date: June 27, 2024Applicant: Advanced Micro Devices, Inc.Inventors: John Kalamatianos, Jagadish B. Kotra, Asmita Pal
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Publication number: 20240214246Abstract: A driver circuit includes a feed-forward equalization (FFE) circuit. The FFE circuit receives a plurality of pulse-amplitude modulation (PAM) symbol values to be transmitted at one of multiple PAM levels. The FFE circuit includes a first partial lookup table, one or more additional partial lookup tables, and an adder circuit. The first partial lookup table contains partial finite impulse-response (FIR) values and indexed based on a current PAM symbol value, a precursor PAM symbol value, and a postcursor PAM symbol value. The one or more additional partial lookup tables each contain partial FIR values and indexed based on a respective additional one or more of the PAM symbol values. The adder circuit adds results of lookups from the first partial lookup table and the additional partial lookup tables to produce an output value.Type: ApplicationFiled: December 22, 2022Publication date: June 27, 2024Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Pradeep Jayaraman, Karthik Gopalakrishnan, Andrew Egli
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Publication number: 20240211142Abstract: Extended training for memory is described. In accordance with the described techniques, a training request to train a memory with extended training is received. The extended training corresponds to a longer amount of time than a default training. The extended training of the memory is performed using a set of target memory settings. In one or more implementations, the extended training is performed during a boot up phase of the computing device.Type: ApplicationFiled: December 27, 2022Publication date: June 27, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Alicia Wen Ju Yurie Leong, Jayesh Hari Joshi, William Robert Alverson, Joshua Taylor Knight, Jerry Anton Ahrens, Amitabh Mehra, Grant Evan Ley
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Publication number: 20240212777Abstract: Memory verification using processing-in-memory is described. In accordance with the described techniques, memory testing logic is loaded into a processing-in-memory component. The processing-in-memory component executes the memory testing logic to test a memory. An indication is output of a detected fault in the memory based on testing the memory.Type: ApplicationFiled: December 27, 2022Publication date: June 27, 2024Applicant: Advanced Micro Devices, Inc.Inventor: Robin Conradine Knauerhase
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Publication number: 20240211399Abstract: A distributed cache network used for machine learning is provided which comprises a network fabric having file systems which store data and a plurality of processing devices, each comprising cache memory and a processor configured to execute a training of a machine learning model and selectively cache portions of the data based on a frequency with which the data is accessed by the processor. Each processing device stores metadata identifying portions of data which are cached in the cache memory and other portions of the data which are cached in other processing devices of the network. When requested data is not cached in another processing device, the portion of requested data is accessed from a network file system via a client to server channel and is accessed from another processing device via a client to client channel when the requested data is cached in the other processing device.Type: ApplicationFiled: December 27, 2022Publication date: June 27, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Kishore Punniyamurthy, Khaled Hamidouche, Brandon Keith Potter
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Publication number: 20240211173Abstract: A memory controller includes an arbiter. The arbiter is configured to elevate a priority of memory access requests that generate row activate commands in response to receiving a same-bank refresh request, and to send a same-bank refresh command in response to receiving the same-bank refresh request.Type: ApplicationFiled: December 22, 2022Publication date: June 27, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Kedarnath Balakrishnan, Jing Wang, Guanhao Shen
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Patent number: 12019876Abstract: A data processor, system, method, integrated circuit are provided which update timing values for accessing a memory to compensate for voltage and temperature (VT) drift during operation. The method includes performing a link retraining sequence for a plurality of DQ lanes of the memory bus and determining a first phase offset based on the link retraining. The method includes calculating a second offset based on the first offset, applying the second offset to a plurality of command CA lanes of the memory bus.Type: GrantFiled: December 12, 2022Date of Patent: June 25, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Aaron D Willey, Karthik Gopalakrishnan, Pradeep Jayaraman
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Patent number: 12019566Abstract: Arbitrating atomic memory operations, including: receiving, by a media controller, a plurality of atomic memory operations; determining, by an atomics controller associated with the media controller, based on one or more arbitration rules, an ordering for issuing the plurality of atomic memory operations; and issuing the plurality of atomic memory operations to a memory module according to the ordering.Type: GrantFiled: July 24, 2020Date of Patent: June 25, 2024Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Sergey Blagodurov, Johnathan Alsop, Jagadish B. Kotra, Marko Scrbak, Ganesh Dasika
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Patent number: 12019879Abstract: Multi-level cell memory management techniques are described. In one example, the memory controller is configured to control whether a single-level cell operation or a multi-level cell operation to be used using different mapping schemes. The single-level cell operation, for instance, is usable to store a data word using two states whereas the multi-level cell operation is usable to store the data word by also using an intermediate state. In order to store the data word using two states, the memory controller is configurable to separate the data word across two word lines in the physical memory. In an implementation, use of the different operations and corresponding mapping schemes by the memory controller alternates between adjacent word lines in physical memory.Type: GrantFiled: September 25, 2022Date of Patent: June 25, 2024Assignee: Advanced Micro Devices, Inc.Inventor: SeyedMohammad SeyedzadehDelcheh
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Patent number: 12019560Abstract: Process isolation for a PIM device includes: receiving, from a process, a call to allocate a virtual address space where the process stores a PIM configuration context; allocating the virtual address space including mapping a physical address space including PIM device configuration registers to the virtual address space only if the physical address space is not mapped to another process's virtual address space; and programming the PIM device configuration space according to the configuration context. When a PIM command is executed, a translation mechanism determines whether there is a valid mapping of a virtual address of the PIM command to a physical address of a PIM resource, such as a LIS entry. If a valid mapping exists, the translation is completed and the resource is accessed, but if there is not a valid mapping, the translation fails and the process is blocked from accessing the PIM resource.Type: GrantFiled: December 20, 2021Date of Patent: June 25, 2024Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Sooraj Puthoor, Muhammad Amber Hassaan, Ashwin Aji, Michael L. Chu, Nuwan Jayasena
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Patent number: 12019904Abstract: One or both of read and write accesses to a fabric-attached memory module via a fabric interconnect are monitored. In one or more implementations, offloading of one or more tasks accessing the fabric-attached memory module to a processor of a routing system associated with the fabric-attached memory module is initiated based on the read and write accesses to the fabric-attached memory module. Additionally or alternatively, replicating memory of the fabric-attached memory module to a cache memory of a computing node in the disaggregated memory system executing one or more tasks of a host application is initiated based on the write accesses to the fabric-attached memory module.Type: GrantFiled: December 15, 2021Date of Patent: June 25, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Vamsee Reddy Kommareddy, Seyedmohammad SeyedzadehDelcheh, Sergey Blagodurov
