Patents Assigned to Advanced Micro Device, Inc.
  • EFFICIENT MEMORY-SEMANTIC NETWORKING USING SCOPED MEMORY MODELS
    Publication number: 20230289070
    Abstract: A framework disclosed herein extends a relaxed, scoped memory model to a system that includes nodes across a commodity network and maintains coherency across the system. A new scope, cluster scope, is defined, that allows for memory accesses at scopes less than cluster scope to operate on locally cached versions of remote data from across the commodity network without having to issue expensive network operations. Cluster scope operations generate network commands that are used to synchronize memory across the commodity network.
    Type: Application
    Filed: May 19, 2023
    Publication date: September 14, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Michael W. LeBeane, Khaled Hamidouche, Hari S. Thangirala, Brandon Keith Potter
  • Method and apparatus for recovering regular access performance in fine-grained DRAM
    Patent number: 11756606
    Abstract: A fine-grained dynamic random-access memory (DRAM) includes a first memory bank, a second memory bank, and a dual mode I/O circuit. The first memory bank includes a memory array divided into a plurality of grains, each grain including a row buffer and input/output (I/O) circuitry. The dual-mode I/O circuit is coupled to the I/O circuitry of each grain in the first memory bank, and operates in a first mode in which commands having a first data width are routed to and fulfilled individually at each grain, and a second mode in which commands having a second data width different from the first data width are fulfilled by at least two of the grains in parallel.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: September 12, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sriseshan Srikanth, Vignesh Adhinarayanan, Jagadish B. Kotra, Sergey Blagodurov
  • Distributed geometry
    Patent number: 11755336
    Abstract: Systems, apparatuses, and methods for performing geometry work in parallel on multiple chiplets are disclosed. A system includes a chiplet processor with multiple chiplets for performing graphics work in parallel. Instead of having a central distributor to distribute work to the individual chiplets, each chiplet determines on its own the work to be performed. For example, during a draw call, each chiplet calculates which portions to fetch and process of one or more index buffer(s) corresponding to one or more graphics object(s) of the draw call. Once the portions are calculated, each chiplet fetches the corresponding indices and processes the indices. The chiplets perform these tasks in parallel and independently of each other. When the index buffer(s) are processed, one or more subsequent step(s) in the graphics rendering process are performed in parallel by the chiplets.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: September 12, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Todd Martin, Tad Robert Litwiller, Nishank Pathak, Randy Wayne Ramsey
  • Efficient rank switching in multi-rank memory controller
    Patent number: 11755246
    Abstract: A data processor includes a staging buffer, a command queue, a picker, and an arbiter. The staging buffer receives and stores first memory access requests. The command queue stores second memory access requests, each indicating one of a plurality of ranks of a memory system. The picker picks among the first memory access requests in the staging buffer and provides selected ones of the first memory access requests to the command queue. The arbiter selects among the second memory access requests from the command queue based on at least a preference for accesses to a current rank of the memory system. The picker picks accesses to the current rank among the first memory access requests of the staging buffer and provides the selected ones of the first memory access requests to the command queue.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: September 12, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Guanhao Shen, Ravindra Nath Bhargava
  • Cache allocation policy
    Patent number: 11755477
    Abstract: A cache includes an upstream port, a downstream port, a cache memory, and a control circuit. The control circuit temporarily stores memory access requests received from the upstream port, and checks for dependencies for a new memory access request with older memory access requests temporarily stored therein. If one of the older memory access requests creates a false dependency with the new memory access request, the control circuit drops an allocation of a cache line to the cache memory for the older memory access request while continuing to process the new memory access request.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: September 12, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Chintan S. Patel, Girish Balaiah Aswathaiya
  • Noise mitigation in single ended links
    Patent number: 11757489
    Abstract: A data transmission system includes a first circuit, a second circuit, and a reference voltage generation circuit. The first circuit includes a transmitter powered by a first power supply voltage and having an input for receiving a data output signal, and an output. The second circuit includes a receiver powered by a second power supply voltage and having a first input coupled to the output of the transmitter, a second input for receiving a reference voltage, and an output for providing a data input signal. The reference voltage generation circuit forms the reference voltage by mixing a first signal generated by the first circuit based on the first power supply voltage and a second signal generated by the second circuit based on the second power supply voltage.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: September 12, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ramon Mangaser, Karthik Gopalakrishnan, Andy Huei Chu, Pradeep Jayaraman
  • Cache line coherence state downgrade
    Patent number: 11755494
    Abstract: Techniques for performing cache operations are provided. The techniques include for a memory access class, detecting a threshold number of instances in which cache lines in an exclusive state in a cache are changed to an invalid state or a shared state without being in a modified state; in response to the detecting, treating first coherence state agnostic requests for cache lines for the memory access class as requests for cache lines in a shared state; detecting a reset event for the memory access class; and in response to detecting the reset event, treating second coherence state agnostic requests for cache lines for the memory class as coherence state agnostic requests.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: September 12, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Paul J. Moyer
  • MEMORY ORGANIZATION FOR MULTI-MODE SUPPORT
    Publication number: 20230280906
    Abstract: A memory package includes first, second, third, and fourth channels arranged consecutively in a clockwise direction on the memory package, each of the first, second, third, and fourth channels having access circuitry and memory arrays. In a first mode, the first channel controls access to the memory arrays in the second channel and the fourth channel controls access to the memory arrays in the third channel.
    Type: Application
    Filed: November 7, 2022
    Publication date: September 7, 2023
    Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Xuan Chen, Ross V. La Fetra, Michael John Litt
  • TECHNIQUE FOR EXTENDED IDLE DURATION FOR DISPLAY TO IMPROVE POWER CONSUMPTION
    Publication number: 20230280819
    Abstract: A method and system for operating in a single display mode operation and a dual pipe mode of operation is disclosed. The method and system includes operating in a dual pipe mode of operation in which each display pipe transmits data from a respective buffer to an associated display. The method and system further includes operating in a single display mode of operation in which one display pipe transmits data from a plurality of buffers to an associated display.
    Type: Application
    Filed: May 12, 2023
    Publication date: September 7, 2023
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Alexander J. Branover, Christopher T. Weaver, Benjamin Tsien, Indrani Paul, Mihir Shaileshbhai Doctor, Thomas J. Gibney, John P. Petry, Dennis Au, Oswin Hall
  • Signalling for heterogeneous memory systems
    Patent number: 11748034
    Abstract: A memory controller selects from among a plurality of memory access commands including volatile memory reads, volatile memory writes, non-volatile memory reads, and non-volatile memory writes. The selected memory access commands are transmitted to a heterogenous memory channel coupled to a non-volatile memory and a volatile memory. The non-volatile read commands that are transmitted are stored in a non-volatile command queue (NV queue). A ready response is received from the non-volatile memory indicating that responsive data is available for an associated one of the non-volatile read commands. In response to receiving the ready response, a send command is transmitted for commanding the non-volatile memory to send the responsive data.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: September 5, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: James R. Magro, Kedarnath Balakrishnan
  • Bounding volume hierarchy traversal
    Patent number: 11748935
    Abstract: A technique for performing ray tracing operations is provided. The technique includes initiating bounding volume hierarchy traversal for a ray against geometry represented by a bounding volume hierarchy; identifying multiple nodes of the bonding volume hierarchy for concurrent intersection tests; and performing operations for the concurrent intersection tests concurrently.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: September 5, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Skyler Jonathon Saleh, Ruijin Wu
  • Method and apparatus for maintaining stable operation of servers in a data center
    Patent number: 11747852
    Abstract: A method and apparatus for managing overclocking in a data center includes determining a frequency limit of a first processor of a first server in the data center. The voltage of the first processor is lowered to a stability point, and the frequency is lowered. The first server is tested for stability. Based upon the results of the test, the voltage and frequency modifications are deployed to a second processor of a second server in the data center.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: September 5, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Amitabh Mehra, Jeffrey N. Burley, Anil Harwani
  • Self-regulating power management for a neural network system
    Patent number: 11748186
    Abstract: A neural network runs a known input data set using an error free power setting and using an error prone power setting. The differences in the outputs of the neural network using the two different power settings determine a high level error rate associated with the output of the neural network using the error prone power setting. If the high level error rate is excessive, the error prone power setting is adjusted to reduce errors by changing voltage and/or clock frequency utilized by the neural network system. If the high level error rate is within bounds, the error prone power setting can remain allowing the neural network to operate with an acceptable error tolerance and improved efficiency. The error tolerance can be specified by the neural network application.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: September 5, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andrew G. Kegel, David A. Roberts
  • High-speed die connections using a conductive insert
    Patent number: 11749629
    Abstract: A semiconductor package for high-speed die connections using a conductive insert, the semiconductor package comprising: a die; a plurality of redistribution layers; a conductive insert housed in a perforation through the plurality of redistribution layers; and a conductive bump conductively coupled to an input/output (I/O) connection point of the die via the conductive insert.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: September 5, 2023
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Rahul Agarwal
  • Artificial neural network emulation of hotspots
    Patent number: 11741397
    Abstract: Methods, devices, and systems for emulating a compute kernel with an ANN. The compute kernel is executed on a processor, and it is determined whether the compute kernel is a hotspot kernel. If the compute kernel is a hotspot kernel, the compute kernel is emulated with an ANN, and the ANN is substituted for the compute kernel.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: August 29, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Nicholas Malaya
  • Memory pools in a memory model for a unified computing system
    Patent number: 11741019
    Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a plurality of processors. The method includes receiving a memory operation from a processor that references an address in a shared memory, mapping the received memory operation to at least one virtual memory pool to produce a mapping result, and providing the mapping result to the processor.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: August 29, 2023
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Anthony Asaro, Kevin Normoyle, Mark Hummel
  • Semiconductor chip with stacked conductor lines and air gaps
    Patent number: 11742289
    Abstract: Various semiconductor chip metallization layers and methods of manufacturing the same are disclosed. In aspect, a semiconductor chip is provided that includes a substrate, plural metallization layers on the substrate, a first conductor line in one of the metallization layers and a second conductor line in the one of the metallization layers in spaced apart relation to the first conductor line, each of the first conductor line and the second conductor line has a first line portion and a second line portion stacked on the first line portion, and a dielectric layer that has a portion positioned between the first conductor line and a second line, the portion has an air gap.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: August 29, 2023
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Richard Schultz
  • Method and apparatus for managing processor functionality
    Patent number: 11740944
    Abstract: A method and apparatus for managing processor functionality includes receiving, by the processor, data relating to one or more environmental conditions. The processor compares the data to pre-existing parameters to determine whether or not the environmental conditions are within the pre-existing parameters for normal operation. If the data are within the pre-existing parameters for normal operation, the processor is operated in a normal operation mode. If the data are outside the pre-existing parameters for normal operation, the processor operates in a second operation mode which is dynamically determined and calibrated during power-on, boot and operation.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: August 29, 2023
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Amitabh Mehra, Anil Harwani, William Robert Alverson, Jerry Anton Ahrens, Jr., Charles Sum Yuen Lee, John William Abshier
  • Fan-out package with reinforcing rivets
    Patent number: 11742301
    Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package is provided that includes a fan-out redistribution layer (RDL) structure that has plural stacked polymer layers, plural metallization layers, plural conductive vias interconnecting adjacent metallization layers of the metallization layers, and plural rivets configured to resist delamination of one or more of the polymer layers. Each of the plural rivets includes a first head, a second head and a shank connected between the first head and the second head. The first head is part of one of the metallization layers. The shank includes at least one of the conductive vias and at least one part of another of the metallization layers.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: August 29, 2023
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Rahul Agarwal, Milind S. Bhagavat, Priyal Shah, Chia-Hao Cheng, Brett P. Wilkerson, Lei Fu
  • Overlapping visibility and render passes for same frame
    Patent number: 11741653
    Abstract: A method of tiled rendering of an image for display is provided which comprises receiving an image comprising one or more three dimensional (3D) objects and executing a visibility pass for determining locations of primitives of the image. The method also comprises executing, concurrently with the executing of the visibility pass, front end geometry processing of one of the primitives determined, from the visibility pass, to be in a first one of a plurality of tiles of the image and executing, concurrently with the executing of the visibility pass, back end processing of the one primitive in the first tile.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: August 29, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mika Tuomi, Ruijin Wu, Anirudh R. Acharya, Kiia Kallio