Patents Assigned to Advanced Micro Device, Inc.
  • Processing unit with small footprint arithmetic logic unit
    Patent number: 11720328
    Abstract: A parallel processing unit employs an arithmetic logic unit (ALU) having a relatively small footprint, thereby reducing the overall power consumption and circuit area of the processing unit. To support the smaller footprint, the ALU includes multiple stages to execute operations corresponding to a received instruction. The ALU executes at least one operation at a precision indicated by the received instruction, and then reduces the resulting data of the at least one operation to a smaller size before providing the results to another stage of the ALU to continue execution of the instruction.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: August 8, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bin He, Shubh Shah, Michael Mantor
  • Automatic memory overclocking
    Patent number: 11720266
    Abstract: Automatic memory overclocking, including: increasing a memory frequency setting for a memory module until a memory stability test fails; determining an overclocked memory frequency setting including a highest memory frequency setting passing the memory stability test; and generating a profile including the overclocked memory frequency setting.
    Type: Grant
    Filed: February 3, 2022
    Date of Patent: August 8, 2023
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: William R. Alverson, Amitabh Mehra, Anil Harwani, Jerry A. Ahrens, Grant E. Ley, Jayesh Joshi
  • Selective generation of miss requests for cache lines
    Patent number: 11720499
    Abstract: A graphics pipeline includes a texture cache having cache lines that are partitioned into a plurality of subsets. The graphics pipeline also includes one or more compute units that selectively generates a miss request for a first subset of the plurality of subsets of a cache line in the texture cache in response to a cache miss for a memory access request to an address associated with the first subset of the cache line. In some embodiments, the cache lines are partitioned into a first sector and a second sector. The compute units generate miss requests for the first sector, and bypass generating miss requests for the second sector, in response to cache misses for memory access requests received during a request cycle being in the first sector.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: August 8, 2023
    Assignees: Advanced Micro Devices, Inc., SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Fataneh Ghodrat, Stephen W. Somogyi, Zhenhong Liu
  • Apparatus and methods for managing packet transfer across a memory fabric physical layer interface
    Patent number: 11720279
    Abstract: An apparatus and method for managing packet transfer between a memory fabric having a physical layer interface higher data rate than a data rate of a physical layer interface of another device, receives incoming packets from the memory fabric physical layer interface wherein at least some of the packets include different instruction types. The apparatus and method determine a packet type of the incoming packet received from the memory fabric physical layer interface and when the determined incoming packet type is of a type containing an atomic request, the method and apparatus prioritizes transfer of the incoming packet with the atomic request over other packet types of incoming packets, to memory access logic that accesses local memory within an apparatus.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: August 8, 2023
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Sergey Blagodurov
  • Hardware-assisted dynamic random access memory (DRAM) row merging
    Patent number: 11721384
    Abstract: Hardware-assisted Dynamic Random Access Memory (DRAM) row merging, including: identifying, by a memory controller, in a DRAM module, a plurality of rows storing identical data; storing, in a mapping table, data mapping one or more rows of the plurality of rows to another row; and excluding the one or more rows from a refresh the DRAM module.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: August 8, 2023
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Jagadish B. Kotra
  • Dynamic kernel memory space allocation
    Patent number: 11720993
    Abstract: A processing unit includes one or more processor cores and a set of registers to store configuration information for the processing unit. The processing unit also includes a coprocessor configured to receive a request to modify a memory allocation for a kernel concurrently with the kernel executing on the at least one processor core. The coprocessor is configured to modify the memory allocation by modifying the configuration information stored in the set of registers. In some cases, initial configuration information is provided to the set of registers by a different processing unit. The initial configuration information is stored in the set of registers prior to the coprocessor modifying the configuration information.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: August 8, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Anthony Gutierrez, Muhammad Amber Hassaan, Sooraj Puthoor
  • DEVICE AND METHOD FOR ACCELERATING MATRIX MULTIPLY OPERATIONS
    Publication number: 20230244751
    Abstract: A processing device is provided which comprises memory configured to store data and a plurality of processor cores in communication with each other via first and second hierarchical communication links. Processor cores of a first hierarchical processor core group are in communication with each other via the first hierarchical communication links and are configured to store, in the memory, a sub-portion of data of a first matrix and a sub-portion of data of a second matrix. The processor cores are also configured to determine a product of the sub-portion of data of the first matrix and the sub-portion of data of the second matrix, receive, from another processor core, another sub-portion of data of the second matrix and determine a product of the sub-portion of data of the first matrix and the other sub-portion of data of the second matrix.
    Type: Application
    Filed: April 7, 2023
    Publication date: August 3, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Shaizeen Aga, Nuwan Jayasena, Allen H. Rush, Michael Ignatowski
  • Efficient memory-semantic networking using scoped memory models
    Patent number: 11714559
    Abstract: A framework disclosed herein extends a relaxed, scoped memory model to a system that includes nodes across a commodity network and maintains coherency across the system. A new scope, cluster scope, is defined, that allows for memory accesses at scopes less than cluster scope to operate on locally cached versions of remote data from across the commodity network without having to issue expensive network operations. Cluster scope operations generate network commands that are used to synchronize memory across the commodity network.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: August 1, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael W. LeBeane, Khaled Hamidouche, Hari S. Thangirala, Brandon Keith Potter
  • Zero operand instruction conversion for accelerating sparse computations in a central processing unit pipeline
    Patent number: 11714652
    Abstract: A processing device includes a zero detection circuit to determine that an operand of a first instruction is zero and instruction conversion logic coupled with the zero detection circuit to, in response to the zero detection circuit determining that the operand is zero, convert the first instruction to a register move instruction executable by the processing device.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: August 1, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John Kalamatianos, Ganesh Dasika
  • Integrated circuit package with integrated voltage regulator
    Patent number: 11715691
    Abstract: Various semiconductor chip devices and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer (RDL) structure having a first plurality of conductor traces, a first molding layer on the first RDL structure, plural conductive pillars in the first molding layer, each of the conductive pillars including a first end and a second end, a second RDL structure on the first molding layer, the second RDL structure having a second plurality of conductor traces, and wherein some of the conductive pillars are electrically connected between some of the first plurality of conductor traces and some of the second plurality of conductor traces to provide a first inductor coil.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: August 1, 2023
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Milind S. Bhagavat, Rahul Agarwal, Chia-Hao Cheng
  • Optimizing primitive shaders
    Patent number: 11715262
    Abstract: A method of deferred vertex attribute shading includes computing, at a graphics processing pipeline of a graphics processing unit (GPU), a plurality of vertex attributes for vertices of each primitive of a set of primitives. The plurality of vertex attributes to be computed includes a vertex position attribute and at least a first non-position attribute for each primitive. One or more primitives of the set of primitives that do not contribute to a rendered image are discarded based upon the vertex position attribute for vertices of the set of primitives. A set of surviving primitives is generated based on the culling and deferred attribute shading is performed for at least a second non-position attribute for vertices of the set of surviving primitives.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: August 1, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Brian J. Favela, Todd Martin, Mangesh P. Nijasure
  • Overlapped curve mapping for histogram-based local tone and local contrast
    Patent number: 11715183
    Abstract: Methods and apparatuses are disclosed herein for performing tone mapping and/or contrast enhancement. In some examples, a block mapping curve is low-pass filtered with block mapping curves of surrounding blocks to form a smoothed block mapping curve. In some examples, overlapped curve mapping of block mapping curves, including smoothed block mapping curves, is performed, including weighting, based on a pixel location, block mapping curves of a group of blocks to generate an interpolated block mapping curve and applying the interpolated block mapping curve to a pixel to perform ton mapping and/or contrast enhancement.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: August 1, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Ying-Ru Chen
  • Pixelation optimized delta color compression
    Patent number: 11715253
    Abstract: A technique for compressing an original image is disclosed. According to the technique, an original image is obtained and a delta-encoded image is generated based on the original image. Next, a segregated image is generated based on the delta-encoded image and then the segregated image is compressed to produce a compressed image. The segregated image is generated because the segregated image may be compressed more efficiently than the original image and the delta image.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: August 1, 2023
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Ruijin Wu, Skyler Jonathon Saleh, Christopher J. Brennan, Kei Ming Kwong, Anthony Hung-Cheong Chan
  • Controlling electrical power consumption for elements in an electronic device based on a platform electrical power limit
    Patent number: 11714442
    Abstract: An electronic device includes an accelerated processing unit (APU) and multiple elements. The APU performs operations for a platform boost and throttle (PBT) controller. For the operations, the APU receives a platform electrical power limit, the platform electrical power limit being a limit on a total electrical power allowed to be consumed by a group of the elements at a given time. The APU then determines a present platform electrical power consumption. The APU next adjusts one or more operating parameters for specified elements from among the group of elements to control electrical power consumption by the specified elements based on a relationship between the present platform electrical power consumption and the platform electrical power limit.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: August 1, 2023
    Assignees: ATI Technologies ULC, Advanced Micro Devices Inc.
    Inventors: Meeta Surendramohan Srivastav, Ashwini Chandrashekhara Holla, Alex Sabino Duenas, Xinzhe Li, Michael John Austin, Indrani Paul, Sriram Sambamurthy
  • Latch bit cells
    Patent number: 11715514
    Abstract: A bit cell of an SRAM implemented using standard cell design rules includes a write portion and a read portion. The write portion includes a pass gate coupled to an input node of the bit cell and supplies data on the input node to a first node of the bit cell while write word line signals are asserted. An inverter is coupled to the first node and supplies inverted data. A keeper circuit that is coupled to the inverter maintains the data on the first node when the write word line signals are deasserted. The read portion of the bit cell receives read word line signals and the inverted data and is responsive to assertion of the read word line signals to supply an output node of the read portion of the bit cell with output data that corresponds to the data on the first node.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: August 1, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Russell J. Schreiber, John J. Wuu
  • Job performance breakdown
    Patent number: 11714739
    Abstract: A system and method for processing application performance using application phase differentiation and detection is disclosed. Phase detection may be accomplished in a number of different ways, including by using a deterministic algorithm that looks for changes in the computing resource utilization patterns (as detected in the performance data collected). Machine learning (ML) and neural networks (e.g. sparse auto encoder SAE) may also be used. Performance data is aggregated according to phase and stored in a database along with additional application and computing system information. This database may then be used to find similar applications for performance prediction.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: August 1, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Max Alt, Gabriel Martin, Paulo Roberto Pereira de Souza filho
  • Allocation of memory access bandwidth to clients in an electronic device
    Patent number: 11709711
    Abstract: An electronic device includes a memory; a plurality of clients; at least one arbiter circuit; and a management circuit. A given client of the plurality of clients communicates a request to the management circuit requesting an allocation of memory access bandwidth for accesses of the memory by the given client. The management circuit then determines, based on the request, a set of memory access bandwidths including a respective memory access bandwidth for each of the given client and other clients of the plurality of clients that are allocated memory access bandwidth. The management circuit next configures the at least one arbiter circuit to use respective memory access bandwidths from the set of memory access bandwidths for the given client and the other clients for subsequent accesses of the memory.
    Type: Grant
    Filed: December 13, 2020
    Date of Patent: July 25, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Guhan Krishnan
  • Wave throttling based on a parameter buffer
    Patent number: 11710207
    Abstract: A graphics pipeline includes a first shader that generates first wave groups, a shader processor input (SPI) that launches the first wave groups for execution by shaders, and a scan converter that generates second waves for execution on the shaders based on results of processing the first wave groups the one or more shaders. The first wave groups are selectively throttled based on a comparison of in-flight first wave groups and second waves pending execution on the at least one second shader. A cache holds information that is written to the cache in response to the first wave groups finishing execution on the shaders. Information is read from the cache in response to read requests issued by the second waves. In some cases, the first wave groups are selectively throttled by comparing how many first wave groups are in-flight and how many read requests to the cache are pending.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: July 25, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christopher J. Brennan, Nishank Pathak
  • Differential pipeline delays in a coprocessor
    Patent number: 11709681
    Abstract: A coprocessor such as a floating-point unit includes a pipeline that is partitioned into a first portion and a second portion. A controller is configured to provide control signals to the first portion and the second portion of the pipeline. A first physical distance traversed by control signals propagating from the controller to the first portion of the pipeline is shorter than a second physical distance traversed by control signals propagating from the controller to the second portion of the pipeline. A scheduler is configured to cause a physical register file to provide a first subset of bits of an instruction to the first portion at a first time. The physical register file provides a second subset of the bits of the instruction to the second portion at a second time subsequent to the first time.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: July 25, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jay Fleischman, Michael Estlick, Michael Christopher Sedmak, Erik Swanson, Sneha V. Desai
  • Fanout module integrating a photonic integrated circuit
    Patent number: 11709327
    Abstract: A semiconductor package includes a first mold layer at least partially encasing at least one photonic integrated circuit. A redistribution layer structure is fabricated on the first mold layer, the redistribution layer structure including dielectric material and conductive structures. A second mold layer at least partially encasing at least one semiconductor chip is fabricated on the redistribution layer structure. The redistribution layer structure provides electrical pathways between the at least one semiconductor chip and the at least one photonic integrated circuit. One or more voids are defined in the second mold layer in an area above an optical interface of the at least one photonic integrated circuit such that light is transmittable through dielectric material above the optical interface.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: July 25, 2023
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Brett P. Wilkerson, Raja Swaminathan, Kong Toon Ng, Rahul Agarwal