Patents Assigned to Advanced Micro Device, Inc.
  • Cache grouping for increasing performance and fairness in shared caches
    Patent number: 11693778
    Abstract: A method includes monitoring one or more metrics for each of a plurality of cache users sharing a cache, and assigning each of the plurality of cache users to one of a plurality of groups based on the monitored one or more metrics.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: July 4, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventor: John Kelley
  • Compressing texture data on a per-channel basis
    Patent number: 11694367
    Abstract: Sampling circuitry independently accesses channels of texture data that represent a set of pixels. One or more processing units separately compress the channels of the texture data and store compressed data representative of the channels of the texture data for the set of pixels. The channels can include a red channel, a blue channel, and a green channel that represent color values of the set of pixels and an alpha channel that represents degrees of transparency of the set of pixels. Storing the compressed data can include writing the compress data to portions of a cache. The processing units can identify a subset of the set of pixels that share a value of a first channel of the plurality of channels and represent the value of the first channel over the subset of the set of pixels using information representing the value, the first channel, and boundaries of the subset.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: July 4, 2023
    Assignees: Advanced Micro Devices, Inc., ATI TECHNOLOGIES ULC
    Inventors: Saurabh Sharma, Laurent Lefebvre, Sagar Shankar Bhandare, Ruijin Wu
  • Detecting execution hazards in offloaded operations
    Patent number: 11693725
    Abstract: Detecting execution hazards in offloaded operations is disclosed. A second offload operation is compared to a first offload operation that precedes the second offload operation. It is determined whether the second offload operation creates an execution hazard on an offload target device based on the comparison of the second offload operation to the first offload operation. If the execution hazard is detected, an error handling operation may be performed. In some examples, the offload operations are processing-in-memory operations.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: July 4, 2023
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Johnathan Alsop, Shaizeen Aga
  • Correcting engagement of a user in a video conference
    Patent number: 11695897
    Abstract: Correcting engagement of a user in a video conference includes: receiving video data of a user of a participant device of a video conference; determining that one or more visual characteristics of the video data satisfy one or more criteria; and displaying, by the participant device, a visual overlay in response to the one or more criteria being satisfied.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: July 4, 2023
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Roto Le
  • Refresh management for memory
    Patent number: 11694739
    Abstract: A memory controller interfaces with a random access memory over a memory channel. A refresh control circuit monitors an activate counter which counts a rolling number of activate commands sent over the memory channel to a memory region of the memory. In response to the activate counter being above an intermediate management threshold value, the refresh control circuit only issue a refresh management (RFM) command if there is no REF command currently held at the refresh command circuit for the memory region.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: July 4, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kevin M. Brandl, Kedarnath Balakrishnan, Jing Wang, Guanhao Shen
  • EMULATING PERFORMANCE OF PRIOR GENERATION PLATFORMS
    Publication number: 20230205680
    Abstract: Methods and systems are disclosed for emulating, in a platform, the performance of a target platform. Techniques disclosed include receiving, by the platform, values of system features, associated with a target performance of the target platform; and setting, by the platform, one or more configuration knobs, based on the received values of system features, to match a performance of the platform to the target performance of the target platform.
    Type: Application
    Filed: December 28, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Richard E. George, Vidyashankar Viswanathan, Michael Y. Chow
  • VARIABLE TICK FOR DRAM INTERFACE CALIBRATION
    Publication number: 20230206973
    Abstract: Methods and systems are disclosed for calibrating, by a memory interface system, an interface with dynamic random-access memory (DRAM) using a dynamically changing training clock. Techniques disclosed comprise receiving a system clock having a clock signal at a first pulse rate. Then, during the training of the interface, techniques disclosed comprise generating a training clock from the clock signal at the first pulse rate, the training clock having a clock signal at a second pulse rate, and sending, based on the generated training clock, command signals, including address data, to the DRAM.
    Type: Application
    Filed: December 29, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Anwar Kashem, Craig Daniel Eaton, Pouya Najafi Ashtiani
  • INLINE SUSPENSION OF AN ACCELERATED PROCESSING UNIT
    Publication number: 20230206379
    Abstract: Methods and systems are disclosed for inline suspension of an accelerated processing unit (APU). Techniques include receiving a packet, including a mode of operation and commands to be executed by the APU; suspending execution of commands received in previous packets when the mode of operation is a suspension initiation mode; and executing, by the APU, the commands in the received packet. The execution of the suspended commands is restored when the mode of operation in a subsequently received packet is a suspension conclusion mode.
    Type: Application
    Filed: December 28, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Alexander Fuad Ashkar, Mangesh P. Nijasure, Rakan Z. Khraisha, Manu Rastogi
  • FEATURE MANAGEMENT FOR MACHINE LEARNING SYSTEM
    Publication number: 20230206113
    Abstract: A technique for processing images is disclosed. The technique includes tracking accesses, by a machine learning system, to individual features of a set of features, to generate an access count for each of the individual features; generating a rank for at least one of the individual features of the set of features based on the access count; and assigning the at least one of the individual features to a level of a memory hierarchy based on the rank.
    Type: Application
    Filed: December 28, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Sergey Blagodurov
  • MULTI-CHIPLET CLOCK DELAY COMPENSATION
    Publication number: 20230205252
    Abstract: Methods and systems are disclosed for clock delay compensation in a multiple chiplet system. Techniques disclosed include distributing, by a clock generator, a clock signal across distribution trees of respective chiplets; measuring phases, by phase detectors, where each phase measurement is associated with a chiplet of the chiplets and is indicative of a propagation speed of the clock signal through the distribution tree of the chiplet. Then, for each chiplet, techniques are further disclosed that determine, by a microcontroller, based on the phase measurements associated with the chiplet, a delay offset, and that delay, based on the delay offset, the propagation of the clock signal through the distribution tree of the chiplet using a delay unit associated with the chiplet.
    Type: Application
    Filed: December 29, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Anwar Kashem, Craig Daniel Eaton, Pouya Najafi Ashtiani, Deepesh John
  • REDUCING POWER CONSUMPTION ASSOCIATED WITH FREQUENCY TRANSITIONING IN A MEMORY INTERFACE
    Publication number: 20230205433
    Abstract: Methods and systems are disclosed for frequency transitioning in a memory interface system. Techniques disclosed include receiving a signal indicative of a change in operating frequency, into a new frequency, in a processing unit interfacing with memory via the memory interface system; switching the system from a normal mode of operation into a transition mode of operation; updating control and state register (CSR) banks of respective transceivers of the system through a mission bus used during the normal mode of operation; and operating the system in the new frequency.
    Type: Application
    Filed: December 29, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Anwar Kashem, Craig Daniel Eaton, Pouya Najafi Ashtiani
  • VARIABLE WIDTH BOUNDING VOLUME HIERARCHY NODES
    Publication number: 20230206542
    Abstract: A technique for performing ray tracing operations is provided. The technique includes processing small bounding box nodes in a box intersection test circuit to generate intersection test results for the small bounding box nodes; and processing large bounding box nodes in the box intersection test circuit to generate intersection test results for the large bounding box nodes.
    Type: Application
    Filed: December 28, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Fataneh F. Ghodrat, Jeffrey Christopher Allan, Skyler Jonathon Saleh
  • FORWARD TENSOR AND ACTIVATION SCALING FOR LOWER PRECISION NEURAL NETWORKS
    Publication number: 20230205544
    Abstract: A processing device is provided which comprises memory configured to store data and a processor configured to execute a forward activation of the neural network using a low precision floating point (FP) format, scale up values of numbers represented by the low precision FP format and process the scaled up values of the numbers as non-zero values for the numbers. The processor is configured to scale up the values of one or more numbers, via scaling parameters, to a scaled up value equal to or greater than a floor of a dynamic range of the low precision FP format. The scaling parameters are, for example, static parameters or alternatively, parameters determined during execution of the neural network.
    Type: Application
    Filed: December 29, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Hai Xiao
  • CONTROL FLOW INVARIANT RESOURCE IDENTIFICATION
    Publication number: 20230205584
    Abstract: A disclosed technique includes allocating a first set of resource slots for a first execution instance of a pipeline shader program; correlating the first set of resource slots with graphics pipeline passes; and on a second execution instance of the pipeline shader program, assigning resource slots, from the first set of resource slots, to the graphics pipeline passes, based on the correlating.
    Type: Application
    Filed: December 28, 2021
    Publication date: June 29, 2023
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Zhuo Chen, Steven J. Tovey
  • BOUNDING VOLUME HIERARCHY BOX NODE COMPRESSION
    Publication number: 20230206540
    Abstract: A technique for performing ray tracing operations is provided. The technique includes combining one or more common exponent values of a compressed box node with one or more minimum vertex mantissas of the compressed box node and one or more maximum vertex mantissas of the compressed box node to obtain one or more minimum vertices and one or more maximum vertices; and combining a minimum vertex of the one or more minimum vertices and a maximum vertex of the one or more maximum vertices to obtain a bounding box for a compressed box data item of the compressed box node.
    Type: Application
    Filed: December 27, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Skyler Jonathon Saleh, Chen Huang
  • BVH NODE ORDERING FOR EFFICIENT RAY TRACING
    Publication number: 20230206539
    Abstract: Methods and systems are disclosed for traversing nodes in a BVH tree by an intersection engine. Techniques disclosed comprise receiving, by the intersection engine, a traversal instruction, including a tracing-mode, ray data, and an identifier of a node to be traversed. Where the tracing-mode includes a closest hit mode and a first hit mode. If the node to be traversed is an internal node, the intersection engine determines, based on the tracing-mode, an order in which children nodes of the node are to be next traversed and output identifiers of the children nodes in the determined order.
    Type: Application
    Filed: December 27, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: John Alexandre Tsakok, Skyler Jonathon Saleh
  • SYSTEMS AND METHOD FOR GENERATING MORTON CODE
    Publication number: 20230206509
    Abstract: Methods and systems are disclosed for encoding a Morton code. Techniques disclosed comprise receiving location vectors associated with primitives, where the primitives are graphical elements spatially located within a three-dimensional scene. Techniques further comprise determining a code pattern comprising a prefix pattern and a base pattern, and, then, coding each of the location vectors according to the code pattern.
    Type: Application
    Filed: December 27, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventor: John Alexandre Tsakok
  • METHOD AND APPARATUS FOR MANAGING POWER STATES
    Publication number: 20230205297
    Abstract: A method and apparatus for managing power states in a computer system includes, responsive to an event received by a processor, powering up a first circuitry. Responsive to the event not being serviceable by the first circuitry, powering up at least a second circuitry of the computer system to service the event.
    Type: Application
    Filed: December 27, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Alexander J. Branover, Thomas J. Gibney, Stephen V. Kosonocky, Mihir Shaileshbhai Doctor, John P. Petry, Indrani Paul, Benjamin Tsien, Christopher T. Weaver
  • DYNAMIC RANDOM-ACCESS MEMORY (DRAM) PHASE TRAINING UPDATE
    Publication number: 20230205435
    Abstract: A phase training update circuit operates during a self-refresh cycle of a memory to perform a phase training update on individual bit lanes. The phase training update circuit adjusts a bit lane transmit phase offset forward a designated number of phase steps, transmits a training pattern, and determines a first number of errors in the transmission. It also adjusts the bit lane transmit phase offset backward the designated number of phase steps, transmits the training pattern, and determines a second number of errors in the transmission. Responsive to a difference between the first number of errors and the second number of errors, the phase training update circuits adjusts a center phase position for the bit lane transmit phase offset of the selected bit lane.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Scott P. Murphy, Huuhau M. Do
  • HARDWARE SUPPORT FOR CONVOLUTION OPERATIONS
    Publication number: 20230206395
    Abstract: A technique for performing convolution operations is disclosed. The technique includes performing a first convolution operation based on a first convolutional layer input image to generate at least a portion of a first convolutional layer output image; while performing the first convolution operation, performing a second convolution operation based on a second convolutional layer input image to generate at least a portion of a second convolutional layer output image, wherein the second convolutional layer input image is based on the first convolutional layer output image; storing the portion of the first convolutional layer output image in a first memory dedicated to storing image data for convolution operations; and storing the portion of the second convolutional layer output image in a second memory dedicated to storing image data for convolution operations.
    Type: Application
    Filed: December 29, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Michael Y. Chow, Vidyashankar Viswanathan, Richard E. George