Patents Assigned to Advanced Micro Device (Shanghai) Co., Ltd.
  • Patent number: 12367145
    Abstract: The disclosed device includes a processor and an interconnect connecting the processor to a memory. The interconnect includes an interconnect agent that can forward memory requests from the processor to the memory and receive requested data returned by the memory. The requested data can include information for a next memory request such that the interconnect agent can send, to the memory, a speculative memory request using information for the next memory request that was received in response to the memory request. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: September 29, 2023
    Date of Patent: July 22, 2025
    Assignees: Advanced Micro Devices, Inc., Xilinx, Inc.
    Inventors: William L. Walker, Scott Thomas Bingham, Pongstorn Maidee, William E. Jones, Richard Carlson
  • Patent number: 12367032
    Abstract: The disclosed device includes a debug circuit and a controller. The debug circuit corresponds to a programmable state machine for responding to trigger conditions based on processor events. The controller is configured to receive a hot loadable patch for a processor firmware, apply the hot loadable patch to reprogram a programmable state machine for monitoring processor events, and run the reprogrammed programmable state machine to monitor the processor events. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: July 22, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Siddharth K. Shah, Viswanath Mohan
  • Patent number: 12367174
    Abstract: A semiconductor module comprises multiple non-homogeneous semiconductor dies disposed on the semiconductor module, with each semiconductor die having a set of circuitry modules that are common to all of the semiconductor dies and also a set of supporting circuitry modules that are distinct between the semiconductor dies. An interconnect communicatively couples the semiconductor dies together. Commands for processing by the semiconductor module may be routed to individual semiconductor dies based on capabilities of the particular circuitry modules disposed on those individual semiconductor dies.
    Type: Grant
    Filed: May 31, 2024
    Date of Patent: July 22, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Matthaeus G. Chajdas
  • Patent number: 12366960
    Abstract: An integrated circuit device includes a memory controller coupleable to a memory. The memory controller to schedule memory accesses to regions of the memory based on memory timing parameters specific to the regions. A method includes receiving a memory access request at a memory device. The method further includes accessing, from a timing data store of the memory device, data representing a memory timing parameter specific to a region of the memory cell circuitry targeted by the memory access request. The method also includes scheduling, at the memory controller, the memory access request based on the data.
    Type: Grant
    Filed: September 22, 2022
    Date of Patent: July 22, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yi Xu, Nuwan S. Jayasena, Yuan Xie
  • Patent number: 12367153
    Abstract: The disclosed method includes detecting a stalled memory request, for a first level cache within a cache hierarchy of a processor, that includes an outstanding memory request associated with a second level cache within the cache hierarchy that is higher than the first level cache. The method further includes indicating, to the second level cache, that the first level cache is experiencing a starvation issue due to stalled memory requests to enable the second level cache to perform starvation-remediation actions. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: July 22, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sankaranarayanan Gurumurthy, Anil Harwani
  • Publication number: 20250231606
    Abstract: Systems, methods, and devices for integrated circuit power management. A mode of a power management state is entered, from the power management state, in response to an entry condition of the mode. A device that is otherwise powered off in the power management state is powered on in the mode of the power management state. In some implementations, the device includes a communications path between a second device and a third device. In some implementations, the device is in a power domain that is powered off in the power management state. In some implementations, the power domain is powered off in the mode. In some implementations, the device is powered on in the mode via a power rail that is specific to the mode. In some implementations, the entry condition of the mode includes an amount of data stored for display in a display buffer falling below a threshold amount.
    Type: Application
    Filed: April 7, 2025
    Publication date: July 17, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Benjamin Tsien, Indrani Paul, Alexander J. Branover, Thomas J. Gibney, Mihir Shaileshbhai Doctor, John P. Petry, Stephen V. Kosonocky, Christopher T. Weaver
  • Patent number: 12360912
    Abstract: An approach provides indirect addressing support for PIM. Indirect PIM commands include address translation information that allows memory modules to perform indirect addressing. Processing logic in a memory module processes an indirect PIM command and retrieves, from a first memory location, a virtual address of a second memory location. The processing logic calculates a corresponding physical address for the virtual address using the address translation information included with the indirect PIM command and retrieves, from the second memory location, a virtual address of a third memory location. This process is repeated any number of times until one or more indirection stop criteria are satisfied. The indirection stop criteria stop the process when work has been completed normally or to prevent errors. Implementations include the processing logic in the memory module working in cooperation with a memory controller to perform indirect addressing.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: July 15, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Matthew R. Poremba, Alexandru Dutu, Sooraj Puthoor
  • Patent number: 12360927
    Abstract: Systems, apparatuses, and methods for implementing duplicated registers for access by initiators across multiple semiconductor dies are disclosed. A system includes multiple initiators on multiple semiconductor dies of a chiplet processor. One of the semiconductor dies is the master die, and this master die has copies of registers which can be accessed by the multiple initiators on the multiple semiconductor dies. When a given initiator on a given secondary die generates a register access, the register access is routed to the master die and a particular duplicate copy of the register maintained for the given secondary die. From the point of view of software, the multiple semiconductor dies appear as a single die, and the multiple initiators appear as a single initiator. Multiple types of registers can be maintained by the master die, with a flush register being one of the register types.
    Type: Grant
    Filed: March 28, 2024
    Date of Patent: July 15, 2025
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Haikun Dong, Kostantinos Danny Christidis, Ling-Ling Wang, Minhua Wu, Gaojian Cong, Rui Wang
  • Patent number: 12360896
    Abstract: Data routing for efficient decompressor use is described. In accordance with the described techniques, a cache controller receives requests from multiple requestors for elements of data stored in a compressed format in a cache. The requests include at least a first request from a first requestor and a second request from a second requestor. A decompression routing system identifies a redundant element of data requested by both the first requestor and the second requestor and causes decompressors to decompress the requested elements of data. The decompression includes performing a single decompression of the redundant element. After the decompression, the decompression routing system routes the decompressed elements to the plurality of requestors, which includes routing the decompressed redundant element to both the first requestor and the second requestor.
    Type: Grant
    Filed: October 25, 2023
    Date of Patent: July 15, 2025
    Assignees: Advanced Micro Devices, Inc., Samsung Electronics Co., Ltd
    Inventors: Jeffrey Christopher Allan, Balakrishnan Sundararaman, Jeongae Park, Wilson Wai Lun Fung, Zhenhong Liu
  • Patent number: 12360907
    Abstract: A method for performing prefetching operations is disclosed. The method includes storing a recorded access pattern indicating a set of accesses for a region; in response to an access within the region, fetching the recorded access pattern; and performing prefetching based on the access pattern.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: July 15, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Gabriel H. Loh, Marko Scrbak, Akhil Arunkumar, John Kalamatianos
  • Patent number: 12353338
    Abstract: A data processing node includes a processor element and a data fabric circuit. The data fabric circuit is coupled to the processor element and to a local memory element and includes a crossbar switch. The data fabric circuit is operable to bypass the crossbar switch for memory access requests between the processor element and the local memory element.
    Type: Grant
    Filed: June 29, 2023
    Date of Patent: July 8, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Gabriel H. Loh
  • Publication number: 20250217298
    Abstract: A method for reducing cache fills can include training a filter, by at least one processor and in response to at least one of eviction or rewrite of one or more entries of a cache, the filter indicating one or more cache loads from which the one or more entries were previously filled. The method can also include preventing, by the at least one processor and based on the trained filter, one or more subsequent fills to the cache from the one or more cache loads. Various other methods and systems are also disclosed.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 3, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Alok Garg, Matthew Sobel, Alice Danielle Kivity
  • Publication number: 20250218104
    Abstract: A device that defines and uses a bounding volume for testing for ray intersections with a displaced micro-mesh. The bounding volume is indirectly based on a twisted prism composed of two triangles and three bilinear patches that bounds the displaced micro-mesh. Instead of detecting intersection with the bilinear patches directly, tetrahedrons that circumscribe the bilinear patches can be used instead. The two bases and the three tetrahedra make fourteen triangles. The device tests for potential intersection with the displaced micro-mesh by testing for an intersection with any of the fourteen triangles. Various other methods and systems are also disclosed.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 3, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: David Kirk McAllister, Andrew Erin Kensler, Holger Gruen
  • Publication number: 20250216889
    Abstract: The disclosed device includes various circuit blocks and a clock tree for sending a clock signal to the circuit blocks. The clock tree includes various clock drivers. The device also includes a control circuit that power gates, in response to one of the circuit blocks being power gated, a portion of the clock tree that includes one of the clock drivers. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 3, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Benjamin Tsien, Pravesh Gupta, Madhusudan Chilakam, Jeffrey Lynn Freeman, Indrani Paul, Guhan Krishnan, Ann M. Ling, Chandana Yerneni
  • Publication number: 20250216888
    Abstract: Temporary system adjustment for component overclocking is described. In accordance with the described techniques, a processor and/or memory are operated according to first settings. During operation of the processor and/or the memory according to the first settings, a signal triggers a temporary adjustment of operation of the processor and/or the memory according to second settings. Responsive to the request, operation of the processor and/or the memory is switched to the second settings without rebooting. After a duration, operation of the processor and/or the memory is switched back to the first settings. In one or more implementations, at least one of the first settings or the second settings overclock the processor and/or the memory.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 3, 2025
    Applicants: Advanced Micro Devices, Inc., ATI TECHNOLOGIES ULC
    Inventors: Wayne Paul Rodrigue, Grant Evan Ley, Jerry Anton Ahrens, JR., Coralie So, Xianglong Du, Nicholas Carmine DeFiore, Ronald James Baughman, Joshua Taylor Knight, William Robert Alverson
  • Publication number: 20250217287
    Abstract: An example device can include at least one network controller configured to receive a data request and to retrieve data based on the data request, and a cache agent configured to receive a data access parameter based on the data request, and reconfigure a cache for at least one memory cache based on the data access parameter. The data request can be received from a computer device and the data can be retrieved from at least one memory device. An example data access parameter can include a latency of at least one network-attached memory device to retrieve data from the at least one memory device based on the data request. An example device can further comprises a flit profiler configured to determine the data access parameter. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 3, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Sergey Blagodurov, Vamsee Reddy Kommareddy, Pratik Mishra, Nathaniel Morris, Kevin Y. Cheng
  • Publication number: 20250217692
    Abstract: A quantum computing device includes a plurality of quantum parallel processing units (Q-PPUs) configured to execute a set of quantum instructions of a quantum application program. The quantum computing device includes an adaptive quantum instruction scheduler to dynamically distribute the set of quantum instructions to the plurality of Q-PPUs based, at least in part, upon a measured probability of a desired result of executing the set of quantum instructions of the quantum application program and a decoherence time of a qubit.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 3, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: DaZheng WANG, Jie ZHANG, Zhenyu XU
  • Publication number: 20250217297
    Abstract: A computing device includes detection circuitry configured to detect invalidation of a line of a cache array. The computing device additionally includes setting circuitry configured to set, in response to the detected invalidation, a spare state encoding in an entry of a partial line-based probe filter that indicates recent invalidation of the line of the cache array. The computing device also includes processing circuitry configured to process a transaction that hits on the entry of the partial line-based probe filter by avoiding a multicast probe of the cache array. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: November 22, 2022
    Publication date: July 3, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Amit P. Apte, Ganesh Balakrishnan
  • Publication number: 20250217292
    Abstract: Adaptive system probe action to minimize input/output dirty data transfers is described. In one or more implementations, a system includes a processor, a memory configured to store data, and a cache configured to store a portion of the data stored in the memory for execution by the processor. The system also includes a cache coherence controller including a cache line history. The cache coherence controller is configured detect a direct memory access request from an input/output device. The direct memory access request is associated with an input/output operation involving the data. The cache coherence controller is further configured to identify a cache line associated with the direct memory access request, and, in response to the cache line history including a dirty data transfer record corresponding to the cache line, selectively send a probe to the cache based on a state of the cache line.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 3, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Li Ou, Ganesh Balakrishnan, Amit Apte
  • Publication number: 20250216456
    Abstract: A system includes a first chiplet and a second chiplet connected via a plurality of interconnects. The system includes a pattern generator configured to generate a test pattern on behalf of the first chiplet. The system includes a pattern checker configured to check the test pattern on behalf of the second chiplet. The system includes a first repair multiplexer and a second repair multiplexer corresponding to the first chiplet and the second chiplet, respectively. The first repair multiplexer and the second repair multiplexer configured to selectively enable a repair path responsive to a short fault between two interconnects of the plurality interconnects based on the checked test pattern.
    Type: Application
    Filed: December 27, 2023
    Publication date: July 3, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Nehal R. Patel, Carl Dean Dietz, Michael Kevin Ciraula, John J. Wuu, Russell J. Schreiber