Abstract: A semiconductor package includes multiple dies that share the same package pin. An output enable register provided on each die is used to select the die that drives an output to the shared pin. A hardware arbitration circuit ensures that two or more dies do not drive an output to the shared pin at the same time.

Abstract: A processing system includes a plurality of processor cores and a plurality of private caches. Each private cache is associated with a corresponding processor core of the plurality of processor cores and includes a corresponding first set of cachelines. The processing system further includes a shared cache shared by the plurality of processor cores. The shared cache includes a second set of cachelines, and a shadow tag memory including a plurality of entries, each entry storing state information for a corresponding cacheline of the first set of cachelines of one of the private caches.

Abstract: The present invention relates to a substrate comprising a build-up and a solder resist layer disposed on the build-up. The solder resist layer has an upper surface facing away from the build-up. The solder resist layer has a plurality of grooves on its upper surface. The grooves of the solder resist layer can better eliminate or relieve the stress accumulated on large solder resist area induced by heat and/or material coefficient of thermal expansion mismatch of the substrate and thus can prevent and diminish warpage of the substrate or package.

Abstract: A system includes a plurality of memory classes and a set of one or more processing units coupled to the plurality of memory classes. The system further includes a data migration controller to select a traffic rate as a maximum traffic rate for transferring data between the plurality of memory classes based on a net benefit metric associated with the traffic rate, and to enforce the maximum traffic rate for transferring data between the plurality of memory classes.

Abstract: A method of manufacturing is provided that includes applying a thermal interface tape to a side of a semiconductor wafer that includes at least one semiconductor chip. The thermal interface material tape is positioned on the at least one semiconductor chip. The at least one semiconductor chip is singulated from the semiconductor wafer with at least a portion of the thermal interface tape still attached to the semiconductor chip.

Abstract: A method and apparatus is provided for monitoring performance of an processor to detect tampering and place the processor in a safe operating state that prevents unauthorized access to contents of the processor. In one example, the method and apparatus compares a measured value of an operating parameter (i.e., a temperature, supply voltage or clock signal) to predefined limits to identify an out of limits measured value. If an out of limits measured value is detected during a normal operating mode, the processor enters a reset mode, and if an out of limits measured value is detected during power up or reset, the processor in retained a reset mode.

Abstract: The present system enables passing a pointer, associated with accessing data in a memory, to an input/output (I/O) device via an input/output memory management unit (IOMMU). The I/O device accesses the data in the memory via the IOMMU without copying the data into a local I/O device memory. The I/O device can perform an operation on the data in the memory based on the pointer, such that I/O device accesses the memory without expensive copies.

Abstract: A method for growing an epitaxial layer patterns a mask over a substrate. The mask protects first areas (N-type areas) of the substrate where N-type field effect transistors (NFETs) are to be formed and exposes second areas (P-type areas) of the substrate where P-type field effect transistors (PFETs) are to be formed. Using the mask, the method can then epitaxially grow the Silicon Germanium layer only on the P-type areas. The mask is then removed and shallow trench isolation (STI) trenches are patterned (using a different mask) in the N-type areas and in the P-type areas. This STI patterning process positions the STI trenches so as to remove edges of the epitaxial layer. The trenches are then filled with an isolation material. Finally, the NFETs are formed to have first metal gates and the PFETs are formed to have second metal gates that are different than the first metal gates. The first metal gates have a different work function than the second metal gates.

Abstract: A strained silicon MOSFET employs a high thermal conductivity insulating material in the trench isolations to dissipate thermal energy generated in the MOSFET and to avoid self-heating caused by the poor thermal conductivity of an underlying silicon germanium layer. The high thermal conductivity material is preferably silicon carbide, and the isolations preferably extend through the silicon germanium layer to contact an underlying silicon layer so as to conduct thermal energy from the active region to the silicon layer.

Abstract: A network switch chip having an expansion port configured for transferring data according to a prescribed bus protocol is tested using an external logic unit (e.g., a field programmable gate array) configured to emulate a connected expansion port. The external logic unit is configured for receiving an expansion port frame from the expansion port via an expansion bus, generating a new expansion port frame, and outputting the new expansion port frame to the expansion port via the expansion bus. Hence, a test engineer can validate the expansion port of the network switch chip by detecting the reception of the new expansion port frame by the expansion port. Hence, the expansion port of the network switch chip can be tested without the necessity of a second network switch chip.

Abstract: A structure for protecting an NROM from induced charge damage during device fabrication is described. The structure provides a discharge path for charge accumulated on the polygate layer during fabrication while providing sufficient isolation to ensure normal circuit operation.

Abstract: A reference cell transistor with a series resistance to improve reliability in reading cells in an associated memory array. The reference cell transistor is coupled in series with a resistive element such that a reference current flows therethrough to reduce a voltage between a gate and a source of the reference cell transistor. This bends the Ids versus Vgate curve of the reference cell downward and compensates for irregularities in the resistance seen in series with the memory cell transistors. In this fashion, the margin when reading memory cells is improved and the reference current is more reliable. The resistive element may be external to a region having the reference cell transistor. Alternatively, the resistive element may be internal to a region with the memory array and reference cell. For example, it may be formed by extending the source region of the reference cell transistor.

Abstract: In the present method of trimming photoresist to form a mask for a layer of a semiconductor device, which layer may include polysilicon and/or nitride, the method is practiced substantially in accordance with: wmin=(h0−Rvtmax)/ARmax where w1=minimum width of trimmed photoresist; h0=height of photoresist prior to trim; Rv=resist vertical etch rate; tmax=maximum etch time to reach resist vertical etch limit; ARmax=maximum allowable aspect ratio of trimmed photoresist.

Abstract: Unacceptable warpage of a tray for holding a plurality of integrated circuit packages is automatically detected after an operator places the tray on a conveyor. The conveyor holds and moves the tray along a predetermined linear path, and the predetermined linear path is along a length of the tray. Each of a plurality of tray position sensors is disposed at a respective location along the predetermined linear. path, and each tray position sensor detects when an object that moves with the conveyor, such as a bracket that is connected to the conveyor, has reached the respective location along the predetermined linear path. A laser beam source is disposed on a first side of the predetermined path for generating a laser beam toward a first side of the tray, and the laser beam has a field that extends through any possible height of the tray.

Abstract: A silicide gate contact is formed which is relatively thicker than silicide contacts formed over source/drain regions and shallow junction extensions. A metal layer is first deposited to form silicide over the polysilicon gate and the source/drain extension regions. The silicide is removed from the extension regions, forming shallow junctions, and a layer of silicide remains on the polysilicon gate. A second metal deposition step and silicidation step forms silicide contacts over the source/drain regions and the polysilicon gate. The resulting silicide gate contact is thicker than the resulting silicide contacts over the source/drain regions.

Abstract: In manufacturing a semiconductor device, an etch stop layer is formed on a cobalt silicide layer during a heat treatment when the cobalt and silicon are transformed in a low resistance phase of cobalt silicide. During a predefined time period, oxygen is added to an inert gas ambient and leads to the formation of silicon oxide on the cobalt silicide. Thus, the present invention avoids a deposition step which would otherwise be necessary for forming the silicon oxide layer on top of the cobalt suicide.

Abstract: A decoder for decoding from two sides of a memory array. The decoder is positioned on two sides of the memory array. The decoder includes driver circuits that are connected to routing lines from the memory array. To reduce the size of the decoder, some of the routing lines extend from one side of the memory array and the remaining routing lines extend from the other side of the memory array.

Abstract: A flash memory (100) includes a core cell array (104), address decoders (116), one or more output buffers (110) and sensing circuitry including sense amplifiers which sense data at an address selected by the address decoders. A data switching multiplexer (108) is coupled to the output buffers to select a sense amplifier for a current word of data in response to a control signal (RWDEN) . A control circuit (106) is coupled to the data switching multiplexer to provide the control signal at a time to ensure the current word of data is provided to the output buffers.

Abstract: Embodiments of the invention comprise a new device and technique to realize an improved temperature control for a chemical photoresist developer utilizing a preexisting integrated single reservoir. This improvement is achieved by providing for a modified temperature control unit and procedure. The temperature control unit preferably comprises a plurality of heat exchanger conduits that are each supplied by an inlet manifold, and then exhausted via an outlet manifold. The temperature control unit preferably extends fully within the modified nozzle unit. By utilizing the improved temperature control unit, a first and second volumetric allocation of developer may be issued so that both may be dispensed within a relatively short period of time upon a photoresist layer surface in a temperature controlled state.

Abstract: A method is provided for selectively electrochemically depositing copper. The method includes forming a layer of dielectric material above a structure layer, forming a conductive layer above the layer of dielectric material and forming an opening in the conductive layer and the layer of dielectric material. The method also includes selectively forming at least one barrier metal layer and a copper seed layer only in the opening, the at least one barrier metal layer and the copper seed layer being conductively coupled to the conductive layer. The method further includes forming an insulating layer above the conductive layer, and selectively electrochemically depositing copper only in the opening.