Patents Assigned to Advanced Micro Device (Shanghai) Co., Ltd.
  • Patent number: 12287739
    Abstract: Address translation is performed to translate a virtual address targeted by a memory request (e.g., a load or memory request for data or an instruction) to a physical address. This translation is performed using an address translation buffer, e.g., a translation lookaside buffer (TLB). One or more actions are taken to reduce data access latencies for memory requests in the event of a TLB miss where the virtual address to physical address translation is not in the TLB. Examples of actions that are performed in various implementations in response to a TLB miss include bypassing level 1 (L1) and level 2 (L2) caches in the memory system, and speculatively sending the memory request to the L2 cache while checking whether the memory request is satisfied by the L1 cache.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: April 29, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jagadish B Kotra, John Kalamatianos
  • Patent number: 12288313
    Abstract: Systems and techniques provide for low-latency, full-frequency noise filtering of images through the use of an image-scaling-based filtering technique, or “multiscale filtering technique”, that can provide filtering for low, medium, and/or high frequencies for one or more components of an image, such that the different resolution scales at each level of the multiscale filtering technique provides a larger receptive field for a denoising process employed at each level than a conventional denoising framework. This multiscale filtering includes receiving an input image to be filtered and then performing a multiscale filtering process in which an input image is, at different resolution scales, denoised, downscaled, upscaled, and fused with a result of a lower resolution scale, to generate a filtered image. This may include temporarily buffering intermediate image data for some of the resolution scales at a memory using direct memory access (DMA) operations.
    Type: Grant
    Filed: December 24, 2021
    Date of Patent: April 29, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: YongMei Dong, Hui Zhou, ZhongFei Dong, Tsung-Han Chiang
  • Patent number: 12288581
    Abstract: A data transmission system includes a first integrated circuit. The first integrated circuit includes a first mixing terminal coupled to a first power supply voltage terminal at a point internal to the first integrated circuit, a first return terminal, a first resistor having a first terminal coupled to the first mixing terminal, and a second terminal for providing a first mixed voltage, and a second resistor having a first terminal coupled to the second terminal of the first resistor, and a second terminal coupled to the first return terminal.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: April 29, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Aaron D Willey, Karthik Gopalakrishnan, Ramon Mangaser
  • Publication number: 20250130774
    Abstract: The disclosed circuit can interpret a bit sequence as a value based on one of multiple floating point number formats in a bias mode indicated by a bias mode indicator. The circuit can and perform an operation using the value in the bias mode. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: December 22, 2023
    Publication date: April 24, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Shubh Shah, Ashutosh Garg, Bin He, Michael Mantor, Shubra Marwaha, Subramaniam Maiyuran
  • Publication number: 20250133133
    Abstract: Embodiments herein describe creating multiple packet fragments from a large data chunk that, for example, exceeds a maximum transmission unit (MTU) supported by a network. In one embodiment, a network interface controller or card (NIC) receives a direct memory access (DMA) from a connected host to transmit an IP packet or data using remote direct memory access (RDMA) technologies. The NIC can evaluate the data chunk associated with the DMA request and determine whether it exceeds the MTU for the network. Assuming it does, the NIC determines how many fragments to divide the data chunk into, and can fragment any portion of the data at flexible packet/payload offsets. The NIC can then retrieve the data chunk from host memory fragment-by-fragment, rather than reading the data chunk all at once, generating headers for the fragments, and then transmit them as packet fragments.
    Type: Application
    Filed: October 19, 2023
    Publication date: April 24, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Raghava SIVARAMU, Vipin JAIN, Rajshekhar BIRADAR
  • Publication number: 20250130769
    Abstract: The disclosed circuit is configured to round a value in a first number format using a random value. Using the rounded value, the circuit can convert the rounded value to a second number format that has a lower precision than a precision of the first number format. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: December 22, 2023
    Publication date: April 24, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Shubh Shah, Ashutosh Garg, Bin He, Michael Mantor, Shubra Marwaha, Subramaniam Maiyuran
  • Publication number: 20250130958
    Abstract: Root-trusted guest memory page management is described. A root-trusted guest is loaded by a hardware platform and authenticated. The root-trusted guest is configured to manage memory operations of different guests via special privileges that permit the root-trusted guest to execute memory operations using a guest's private memory page. To do so, a guest page table includes a novel “T-bit” in each entry, which indicates whether the root-trusted guest or a different guest owns the associated memory page. Each entry in the guest page table for the root-trusted guest additionally includes a “C-bit” that indicates whether the corresponding memory page is a protected page. Combined C-bit and T-bit values for a page table entry dictate whether operations performed as part of handling a guest's memory request are offloaded from the hardware platform to the root-trusted guest.
    Type: Application
    Filed: October 24, 2024
    Publication date: April 24, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Reshma Lal, David A. Kaplan, Jelena Ilic
  • Publication number: 20250130936
    Abstract: A memory controller includes a command queue stage, an arbitration stage, and a dispatch queue. The command queue stage stores decoded memory access requests. The arbitration stage is operable to select first and second memory commands from the command queue stage for first and second pseudo-channels, respectively, using a shred resource. The dispatch queue has first and second upstream ports for receiving the first and second memory commands, and a downstream port for conducting first data of the first memory commands time-multiplexed with second data of the second memory commands.
    Type: Application
    Filed: March 28, 2024
    Publication date: April 24, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: James R. Magro, Kedarnath Balakrishnan
  • Publication number: 20250130794
    Abstract: The disclosed processing circuit can perform an operation with a first operand having a first number format and a second operand having a second number format by directly using the first operand in the first number format and the second operand in the second number format to produce an output result. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 24, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Shubh Shah, Ashutosh Garg, Bin He, Michael Mantor, Shubra Marwaha, Subramaniam Maiyuran
  • Publication number: 20250130844
    Abstract: A security framework for virtual machines is described. In one or more implementations, a hardware platform comprises physical computer hardware, the physical computer hardware including one or more processing units and one or more memories. The system also includes a virtual machine monitor configured to virtualize the physical computer hardware of the hardware platform to instantiate a plurality of framework-secure virtual machines. Further, the system includes a root framework-secure virtual machine instantiated by the virtual machine monitor. In accordance with the described techniques, the root framework-secure virtual machine is configured to control access to the hardware platform by the framework-secure virtual machines instantiated by the virtual machine monitor.
    Type: Application
    Filed: October 24, 2024
    Publication date: April 24, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Reshma Lal, David A. Kaplan, Jelena Ilic
  • Publication number: 20250130767
    Abstract: The disclosed circuit can select micro-operations specifically for converting a value in a first number format to a second number format. The circuit can include micro-operations for various conversions between different number formats, including number formats of different floating-point precisions. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: October 21, 2024
    Publication date: April 24, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Shubh Shah, Ashutosh Garg, Bin He, Michael Mantor, Shubra Marwaha, Subramaniam Maiyuran
  • Publication number: 20250130715
    Abstract: A system includes memory hardware including a memory and a processing-in-memory component. A system includes a host including at least one core. A system includes a memory controller including a scheduling system. The scheduling system transforms an all-bank processing-in-memory command into multiple masked processing-in-memory commands. The scheduling system also schedules the multiple masked processing-in-memory commands to the processing-in-memory component.
    Type: Application
    Filed: October 18, 2023
    Publication date: April 24, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Vignesh Adhinarayanan, Shaizeen Dilawarhusen Aga
  • Patent number: 12282428
    Abstract: In response to generating one or more speculative prefetch requests for a last-level cache, a processor determines prefetch analytics for the generated speculative prefetch requests and compares the determined prefetch analytics of the speculative prefetch requests to selection thresholds. In response to a speculative prefetch request meeting or exceeding a selection threshold, the processor selects the speculative prefetch request for issuance to a memory-side cache controller. When one or more system conditions meet one or more condition thresholds, the processor issues the selected speculative prefetch request to the memory-side cache controller. The memory-side cache controller then retrieves the data indicated in the selected speculative prefetch request from a memory and stores it in a memory-side cache in the data fabric coupled to the last-level cache.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: April 22, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Tarun Nakra, Akhil Arunkumar, Paul Moyer, Jay Fleischman
  • Patent number: 12284116
    Abstract: Systems, apparatuses, and methods for dynamic buffer management in multi-client token flow control routers are disclosed. A system includes at least one or more processing units, a memory, and a communication fabric with a plurality of routers coupled to the processing unit(s) and the memory. A router servicing multiple active clients allocates a first number of tokens to each active client. The first number of tokens is less than a second number of tokens needed to saturate the bandwidth of each client to the router. The router also allocates a third number of tokens to a free pool, with tokens from the free pool being dynamically allocated to different clients. The third number of tokens is equal to the difference between the second number of tokens and the first number of tokens. An advantage of this approach is reducing the amount of buffer space needed at the router.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: April 22, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alan Dodson Smith, Chintan S. Patel, Eric Christopher Morton, Vydhyanathan Kalyanasundharam, Narendra Kamat
  • Patent number: 12284447
    Abstract: A method and apparatus for normalizing an image in an image capturing device includes receiving a processed image by the image device. The processed image is brightness normalized to create a brightness normalized image. The brightness normalized image is provided to an artificial intelligence engine for processing.
    Type: Grant
    Filed: November 16, 2022
    Date of Patent: April 22, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Chang-Chiang Lin
  • Patent number: 12282439
    Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. When a memory controller in a computing system determines a threshold number of memory access requests have not been sent to the memory device in a current mode of a read mode and a write mode, a first cost corresponding to a latency associated with sending remaining requests in either the read queue or the write queue associated with the current mode is determined. If the first cost exceeds the cost of a data bus turnaround, the cost of a data bus turnaround comprising a latency incurred when switching a transmission direction of the data bus from one direction to an opposite direction, then a second cost is determined for sending remaining memory access requests to the memory device. If the second cost does not exceed the cost of the data bus turnaround, then a time for the data bus turnaround is indicated and the current mode of the memory controller is changed.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: April 22, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Guanhao Shen, Ravindra N. Bhargava, Kedarnath Balakrishnan
  • Publication number: 20250124649
    Abstract: A technique for rendering is provided. The technique includes obtaining one or more samples for a pixel, the samples obtained for a microfacet surface from a spherical cap cut off by a lower plane positioned to exclude reflected rays that are occluded by the microfacet surface; obtaining one or more contributions corresponding to the one or more samples; determining a color for the pixel based on the one or more contributions.
    Type: Application
    Filed: October 17, 2023
    Publication date: April 17, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Yusuke Tokuyoshi, Kenta Eto
  • Publication number: 20250124206
    Abstract: Dynamic voltage drop analysis for a circuit design includes generating, by computer hardware, bias information for a circuit design. The bias information specifies switching information for a plurality of instances of one or more standard cells of the circuit design. A schedule specifying switching for the plurality of instances of the circuit design is generated by the computer hardware based on the bias information. A dynamic voltage analysis is performed by the computer hardware on the circuit design to generate dynamic voltage analysis results by switching the plurality of instances of the circuit design based on the schedule.
    Type: Application
    Filed: October 16, 2024
    Publication date: April 17, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Antonio R. Todesco, Prashanth Muthu Swamy, Hariram Ravindran, Khoa D. Nguyen
  • Publication number: 20250123761
    Abstract: A data processor includes a memory controller and a physical interface circuit coupled to the memory controller. In response to a system startup, the memory controller controls the physical interface circuit to selectively train a memory based on whether a first memory clock frequency of a plurality of power states equals any other memory clock frequency of the plurality of power states.
    Type: Application
    Filed: October 17, 2023
    Publication date: April 17, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Xianglong Du, Kai-Chieh Chan, Haibin Niu
  • Publication number: 20250123846
    Abstract: A processing unit includes a plurality of processing cores and is configured to arrange a sparse matrix for parallel performance by the cores on different rows of the matrix at least in part by calculating a respective quantity of non-zero elements in each row, assigning each row to a respective collection according to the respective quantity of non-zero elements for the row, wherein the processing unit is configured to assign at least one first row of the sparse matrix to respective collections of in parallel with assigning at least one second row of the sparse matrix to respective collections, and performing at least one mathematical operation on at least a first collection of the plurality of collections in parallel with performing the at least one mathematical operation on at least a second collection of the plurality of collections.
    Type: Application
    Filed: October 12, 2023
    Publication date: April 17, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: William Peter Ehrett, Muhammad Osama, Bradford Beckmann