Abstract: A memory request issue counter (MRIC) is maintained that is incremented for every memory access a central processing unit core makes. A region reuse distance table is also maintained that includes multiple entries each of which stores the region reuse distance for a corresponding region. When a memory access request for a physical address is received, a reuse distance for the physical address is calculated. This reuse distance is the difference between the current MRIC value and a previous MRIC value for the physical address. The previous MRIC value for the physical address is the MRIC value the MRIC had when a memory access request for the physical address was last received. A region reuse distance for a region that includes the physical address is generated based on the reuse distance for the physical address and used to manage the cache.

Abstract: Methods, apparatuses, and computer-readable medium for incorporating motion awareness into the decision-making process of automatic exposure (AE) to prevent noticeable image quality deterioration resulting from motion blur. In some instances, by harnessing the capabilities of integrated camera Image Signal Processors (ISP), Inference Processing Unit (IPU), and/or Artificial Intelligent (AI) acceleration, the described methods, apparatuses, and computer-readable medium may achieve optimal computational efficiency and enhanced image quality.

Abstract: A cache cleaner controller is described. In one or more examples, an apparatus includes a cache directory including status bits associated with cache locations within cache storage and a cache cleaner controller. The cache cleaner controller is configured to detect that a cache cleaner threshold has been reached. The cache cleaner threshold defines that a threshold number of the status bits indicate data maintained at the cache locations, respectively, has been changed. The cache cleaner controller is also configured to cause the data indicated as changed by the status bits to be copied from the cache locations within cache storage to the physical volatile memory.

Abstract: Matrix-fused min-add (MFMA) instructions are described. The MFMA instructions cause a processing device to execute at least one of a min-plus function or a plus-min function. The MFMA instructions cause the processor device to execute min-plus and plus-min functions in response to a single instruction and without performing a multiplication operation as required by conventional systems. In accordance with the described techniques, a MFMA instruction causes multiple logic units (e.g., threads or wavefronts) of a processing device to execute a min-plus function, a plus-min function, or combinations thereof, as part of completing a computational task. To optimize system efficiency, the MFMA instruction causes the processing device to execute the min-plus function, the plus-min function, or combinations thereof using data stored in local registers of the processor device.

Abstract: Systems, apparatuses, and methods for reducing probe filter accesses in response to processing-in-memory (PIM) requests are disclosed. A coherent secondary unit receives PIM requests targeting a corresponding PIM device. For each PIM request that is received, the coherent secondary unit performs a lookup of a PIM address table (PAT). If the address of the PIM request matches an address of an existing entry in the PAT, the coherent secondary unit prevents the PIM request from being sent to a probe filter. Otherwise, if there is no match for the address of the PIM request in the entries of the PAT, the coherent secondary unit sends the PIM request to the probe filter, and the coherent secondary unit creates a new PAT entry for the address of the PIM request. Any subsequent PIM requests to the same address will match with the new entry in the PAT.

Abstract: The disclosed semiconductor package includes a first chiplet area for receiving a first chiplet, a second chiplet area for receiving a second chiplet, and a host die coupled to the first and second chiplet areas. The semiconductor package also includes an interconnect directly coupling the first chiplet area to the second chiplet area. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A data processor is adapted to couple to a memory. The data processor includes a memory operation array, a power engine, and an initialization circuit. The memory operation array includes a command portion and a data portion. The power engine has an input for receiving power state change request signals and an output for providing memory operations responsive to instructions stored in the command portion. The initialization circuit populates the data portion such that consecutive memory operations are separated by an amount corresponding to a predetermined minimum timing parameter.

Abstract: According to one aspect, a system includes a processor core, a history buffer, a history buffer logic, and an interrupt controller. The processor core is configured to issue a trigger that causes the history buffer logic to, after a fixed time, flush existing entries in the history buffer and start adding new entries into the history buffer. According to another aspect, a system includes a processor core that includes a load store tracker buffer and a prefetch engine. The buffer is configured to track a critical section memory location associated with critical section data fetched by the processor core. The prefetch engine is configured to obtain the critical section memory location from a previous load store tracker buffer associated with a previous lock holder processor core. The system also includes a lock manager configured to signal the buffer to start and stop tracking the critical section memory.

Abstract: A disclosed method may include initializing a deep learning recommendation model (DLRM) comprising a plurality of embedding tables, each embedding table comprising a plurality of embeddings. The method may also include receiving input data associated with accessing embeddings from the plurality of embedding tables and applying a parallelization strategy to process the plurality of embedding tables, the parallelization strategy configured to improve performance by distributing computational workloads and optimizing memory access. The method may also include processing the embeddings based on the input data in accordance with the parallelization strategy, the processing comprising aggregating embeddings accessed from the plurality of embedding tables. The method may also include generating, for further processing, output data based on the processed embeddings. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: The disclosed computer-implemented method includes transforming, from a time domain into a frequency domain, a sound signal into a transformed sound signal. The transformed sound signal has a phase component and a magnitude component. The method also includes filtering the phase component of the transformed sound signal by applying a quantized mask from a machine-learning model to the phase component, and generating a filtered sound signal by transforming, from the frequency domain into the time domain, the transformed sound signal comprising the magnitude component and the filtered phase component. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: The disclosed device can include a dual-tail sampler. The dual-tail sampler can include a first stage with an input pair, a cross-coupled load circuit, a precharge device between drain nodes of the input pair, and at least one pass-gate switch between the input pair and the cross-coupled load circuit. Various other devices and systems are also disclosed.

Abstract: Disclosed is a computer-implemented method for degassing for the manufacture of a high speed design. The method includes analyzing information related to a printed circuit board (PCB) that includes a set of layers and a plurality of voids. The method identifies a void from the plurality of voids, where the void has a position among the PCB set of layers. The method determines a radius associated with the identified void, where the radius is based on a center of the identified void. The method performs a trace selection and executes a shift algorithm based on the trace selection, where the shift algorithm includes a modification of the information related to the void. As a result, the method can generate a grid for degassing based on execution of the shift algorithm. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A technique is provided. The technique includes identifying memory cells, of a set of memory cells to power down, based on a set of priorities for the set of memory cells; powering down the identified memory cells in accordance with the set of priorities, resulting in powered down memory cells; and performing processing in accordance with the powered down memory cells.

Abstract: A semiconductor device includes a first metal layer including a plurality of first ground wire pairs alternating with a plurality of first power wire pairs and a second metal layer including a plurality of second ground wire pairs alternating with a plurality of second power wire pairs. A metal-insulator-metal capacitor (MIMCAP) is between the first metal layer and the second metal layer. A group of ground vias connects a pair of the first ground wire pairs with a pair of the second ground wire pairs. The group of ground vias can also connect to a ground plate of the MIMCAP. A group of power vias connects a pair of the first power wire pairs with a pair of the second power wire pairs. The group of power vias can also connect to a power plate of the MIMCAP. Various other methods and systems are also disclosed.

Abstract: A memory device includes a memory circuitry includes a first transmission grate, a first capacitor, a second transmission gate, and a second capacitor. The first transmission gate includes a first transistor connected between a first node and a second node. The first transistor having a gate terminal connected to a first clock node. The first clock node configured to receive a first clock signal. The first capacitor is connected between the second node and a first voltage node. The first capacitor is a ferroelectric capacitor. The second transmission gate includes a second transistor connected between the second node and a third node. The second transistor has a gate terminal connected to the first clock node. The second capacitor is connected between the third node and a second voltage node.

Abstract: A static random-access memory (SRAM) circuit includes an SRAM bitcell coupled to a word line, a bit line and a complementary bit line. A precharge circuit is coupled to the bit line and the complementary bit line and includes a precharge input. A first keeper transistor is coupled to the bit line and a second keeper transistor is coupled to the complementary bit line. A write driver circuit includes a select input receiving a select signal, a write data input, and a write data compliment input, and is operable to write a data bit to the SRAM bitcell. A combinatorial logic circuit provides a precharge signal to the precharge circuit based on the select signal and a bit line precharge signal.

Abstract: A semiconductor device includes a first logic die comprising: a clock source configured to generate a clock signal; and a first clock mesh for receiving the clock signal from the clock source. The device includes a second logic die stacked over the first logic die, the second logic die comprising: a second clock mesh for receiving the clock signal from the clock source. The device includes a plurality of conductive connections between the first clock mesh and the second clock mesh to transmit the clock signal from the first clock mesh to the second clock mesh. Various other methods and systems are also disclosed.

Abstract: Task graph control techniques for data transfer are described. The task graph control techniques are usable to aggregate data from multiple tasks into an aggregated data transfer, thereby improving operational efficiency and device performance. In a first example, a runtime scheduler executed on a command processor is implemented to select a node during execution of tasks of the task graph. The selected node is assigned by the runtime schedule to transfer aggregated data from that node and parent of that node. In a second example, a compiler of a host device is tasked with generating the task graph. As part of generating the task graph, the compiler also inserts one or more data transfer nodes. The location of the data transfer node within the task graph by the compiler is used to specify when a data transfer is to be performed.

Abstract: A technique for performing inside/outside testing is provided. To determine if a ray intersects a convex polygon, an inside/outside test is commonly performed by checking which side of an edge the ray passes. By efficiently sharing edge test results among polygons with shared edges, inside/outside testing for groups of polygons can be made more efficient. This optimization can be achieved using either full precision floating-point math or reduced precision (e.g., fixed-point math) to make hardware-based testing more cost-effective.

Abstract: A computer-implemented method for hardware gather optimization can include identifying, by at least one processor, one or more gather instructions that retrieve data from contiguous memory locations. The method can additionally include converting, by the at least one processor, the one or more gather instructions into one or more strided load instructions in response to the identification. The method can also include loading, by the at least one processor, data retrieved using the one or more strided load instructions into one or more vector registers. Various other methods, systems, and computer-readable media are also disclosed.