Patents Assigned to ADVANCED MICRO DEVICES (AMD)
  • Method and apparatus for asynchronous scheduling
    Patent number: 11023242
    Abstract: A method and apparatus of asynchronous scheduling in a graphics device includes sending one or more instructions from an instruction scheduler to one or more instruction first-in/first-out (FIFO) devices. An instruction in the one or more FIFO devices is selected for execution by a single-instruction/multiple-data (SIMD) pipeline unit. It is determined whether all operands for the selected instruction are available for execution of the instruction, and if all the operands are available, the selected instruction is executed on the SIMD pipeline unit. The self-timed arithmetic pipeline unit (SIMD pipeline unit) is effectively encapsulated in a synchronous, (e.g., clocked by global clock), scheduler and register file environment.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: June 1, 2021
    Assignees: ATI TECHNOLOGIES ULC, ADVANCED MICRO DEVICES, INC.
    Inventors: John Kalamatianos, Greg Sadowski, Syed Zohaib M. Gilani
  • Instructions for performing multi-line memory accesses
    Patent number: 11023410
    Abstract: A system is described that performs memory access operations. The system includes a processor in a first node, a memory in a second node, a communication interconnect coupled to the processor and the memory, and an interconnect controller in the first node coupled between the processor and the communication interconnect. Upon executing a multi-line memory access instruction, the processor prepares a memory access operation for accessing, in the memory, a block of data including at least some of each of at least two lines of data. The processor then causes the interconnect controller to use a single remote direct memory access memory transfer to perform the memory access operation for the block of data via the communication interconnect.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: June 1, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: David A. Roberts, Shenghsun Cho
  • Multi-chip package with offset 3D structure
    Patent number: 11018125
    Abstract: Various semiconductor chip devices and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that has a reconstituted semiconductor chip package that includes an interposer that has a first side and a second and opposite side and a metallization stack on the first side, a first semiconductor chip on the metallization stack and at least partially encased by a dielectric layer on the metallization stack, and plural semiconductor chips positioned over and at least partially laterally overlapping the first semiconductor chip.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: May 25, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Milind S. Bhagavat, Rahul Agarwal, Gabriel H. Loh
  • Integrated circuit package with integrated voltage regulator
    Patent number: 11011466
    Abstract: Various semiconductor chip devices and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer (RDL) structure having a first plurality of conductor traces, a first molding layer on the first RDL structure, plural conductive pillars in the first molding layer, each of the conductive pillars including a first end and a second end, a second RDL structure on the first molding layer, the second RDL structure having a second plurality of conductor traces, and wherein some of the conductive pillars are electrically connected between some of the first plurality of conductor traces and some of the second plurality of conductor traces to provide a first inductor coil.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: May 18, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Milind S. Bhagavat, Rahul Agarwal, Chia-Hao Cheng
  • Reduced bandwidth tessellation factors
    Patent number: 11010862
    Abstract: A graphics pipeline reduces the number of tessellation factors written to and read from a graphics memory. A hull shader stage of the graphics pipeline detects whether at least a threshold percentage of the tessellation factors for a thread group of patches are the same and, in some embodiments, whether at least the threshold percentage of the tessellation factors for a thread group of patches have a same value that either indicates that the plurality of patches are to be culled or that the plurality of patches are to be passed to a tessellator stage of the graphics pipeline.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: May 18, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Mangesh P. Nijasure, Tad Litwiller, Todd Martin, Nishank Pathak
  • Networked input/output memory management unit
    Patent number: 11003588
    Abstract: A networked input/output memory management unit (IOMMU) includes a plurality of IOMMUs. The networked IOMMU receives a memory access request that includes a domain physical address generated by a first address translation layer. The networked IOMMU selectively translates the domain physical address into a physical address in a system memory using one of the plurality of IOMMUs that is selected based on a type of a device that generated the memory access request. In some cases, the networked IOMMU is connected to a graphics processing unit (GPU), at least one peripheral device, and the memory. The networked IOMMU includes a command queue to receive the memory access requests, a primary IOMMU to selectively translate the domain physical address in memory access requests from the GPU, and a secondary IOMMU to translate the domain physical address in memory requests from the peripheral device.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: May 11, 2021
    Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Sonu Arora, Paul Blinzer, Philip Ng, Nippon Harshadk Raval
  • Automatic configuration of knobs to optimize performance of a graphics pipeline
    Patent number: 11004251
    Abstract: A knob has a plurality of settings that configure a graphics pipeline. A first setting is associated with a first state of the graphics pipeline. The first setting is associated with the first state based on a measure of performance of the graphics pipeline while configured according to the first setting. The graphics pipeline is configured according to the first setting in response to the first state of the graphics pipeline matching a current state of the graphics pipeline. The graphics pipeline processes graphics according to the first setting. In some cases, the first setting is associated with the first state of the graphics pipeline by dithering or toggling the knob between the settings once per frame for a predetermined number of frames. The first setting achieves better performance than other ones of the plurality of settings during the predetermined number of frames.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: May 11, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Christopher J. Brennan
  • Semiconductor chip with stacked conductor lines and air gaps
    Patent number: 11004791
    Abstract: Various semiconductor chip metallization layers and methods of manufacturing the same are disclosed. In aspect, a semiconductor chip is provided that includes a substrate, plural metallization layers on the substrate, a first conductor line in one of the metallization layers and a second conductor line in the one of the metallization layers in spaced apart relation to the first conductor line, each of the first conductor line and the second conductor line has a first line portion and a second line portion stacked on the first line portion, and a dielectric layer that has a portion positioned between the first conductor line and a second line, the portion has an air gap.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: May 11, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Richard Schultz
  • METHOD AND APPARATUS FOR DATA SCRAMBLING
    Publication number: 20210132675
    Abstract: A method and apparatus for scrambling and descrambling data in a computer system includes transmitting non-scrambled data from a first high speed inter chip (IP) link circuit located on a first chip to a first serializer/deserializer (SERDES) physical (PHY) circuit located on the first chip, the first high speed link IP indicating the data is not scrambled. The received non-scrambled data is scrambled by the first SERDES PHY circuit and transmitted to a second chip. The received scrambled data is descrambled by a second SERDES PHY circuit located on the second chip. The non-scrambled data is transmitted by the second SERDES PHY circuit to a second high speed link IP circuit located on the second chip to a third circuit for further processing or transmission.
    Type: Application
    Filed: January 15, 2021
    Publication date: May 6, 2021
    Applicants: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Yanfeng Wang, Michael J. Tresidder, Kevin M. Lepak, Larry David Hewitt, Noah Beck
  • Address-based filtering for load/store speculation
    Patent number: 10990393
    Abstract: Address-based filtering for load/store speculation includes maintaining a filtering table including table entries associated with ranges of addresses; in response to receiving an ordering check triggering transaction, querying the filtering table using a target address of the ordering check triggering transaction to determine if an instruction dependent upon the ordering check triggering transaction has previously been generated a physical address; and in response to determining that the filtering table lacks an indication that the instruction dependent upon the ordering check triggering transaction has previously been generated a physical address, bypassing a lookup operation in an ordering violation memory structure to determine whether the instruction dependent upon the ordering check triggering transaction is currently in-flight.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: April 27, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: John Kalamatianos, Krishnan V. Ramani, Susumu Mashimo
  • Residency map descriptors
    Patent number: 10991146
    Abstract: A processor receives a request to access one or more levels of a partially resident texture (PRT) resource. The levels represent a texture at different levels of detail (LOD) and the request includes normalized coordinates indicating a location in the texture. The processor accesses a texture descriptor that includes dimensions of a first level of the levels and one or more offsets between a reference level and one or more second levels that are associated with one or more residency maps that indicate texels that are resident in the PRT resource. The processor translates the normalized coordinates to texel coordinates in the one or more residency maps based on the offset and accesses, in response to the request, the one or more residency maps based on the texel coordinates to determine whether texture data indicated by the normalized coordinates is resident in the PRT resource.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: April 27, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Maxim V. Kazakov, Mark Fowler
  • Interposer-based damping resistor
    Patent number: 10985097
    Abstract: Various resistor circuits and methods of making and using the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a resistor onboard an interposer. The resistor is adapted to dampen a capacitive network. The capacitive network has at least one capacitor positioned external to the interposer.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: April 20, 2021
    Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Fei Guo, Feng Zhu, Julius Din, Anwar Kashem, Sally Yeung
  • Interconnect architecture for three-dimensional processing systems
    Patent number: 10984838
    Abstract: A processing system includes a plurality of processor cores formed in a first layer of an integrated circuit device and a plurality of partitions of memory formed in one or more second layers of the integrated circuit device. The one or more second layers are deployed in a stacked configuration with the first layer. Each of the partitions is associated with a subset of the processor cores that have overlapping footprints with the partitions. The processing system also includes first memory paths between the processor cores and their corresponding subsets of partitions. The processing system further includes second memory paths between the processor cores and the partitions.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: April 20, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Nuwan S. Jayasena, Yasuko Eckert
  • Using age matrices for managing entries in sub-queues of a queue
    Patent number: 10963402
    Abstract: An electronic device includes a queue with multiple sub-queues arranged in a logical hierarchy from a lowest sub-queue to a highest sub-queue, each sub-queue including a separate subset of a set of entries of the queue, and a separate age matrix for each sub-queue. The electronic device also includes a controller that stores items in entries in the lowest sub-queue until the lowest sub-queue is full and then stores items in successively next higher sub-queues in the hierarchy. The controller also removes an item that is ready for removal from an entry in the lowest sub-queue. The controller then shifts items in sub-queues in the hierarchy to fill the vacancy in the lowest sub-queue. For the shifting, the controller uses an age matrix associated with each sub-queue to determine an oldest item in that sub-queue and then moves the oldest item to a next lower sub-queue in the hierarchy.
    Type: Grant
    Filed: December 28, 2019
    Date of Patent: March 30, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Gregg Donley, Mark Silla
  • Hardware accelerated dynamic work creation on a graphics processing unit
    Patent number: 10963299
    Abstract: A processor core is configured to execute a parent task that is described by a data structure stored in a memory. A coprocessor is configured to dispatch a child task to the at least one processor core in response to the coprocessor receiving a request from the parent task concurrently with the parent task executing on the at least one processor core. In some cases, the parent task registers the child task in a task pool and the child task is a future task that is configured to monitor a completion object and enqueue another task associated with the future task in response to detecting the completion object. The future task is configured to self-enqueue by adding a continuation future task to a continuation queue for subsequent execution in response to the future task failing to detect the completion object.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: March 30, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Anthony Gutierrez, Sooraj Puthoor
  • Memory system with region-specific memory access scheduling
    Patent number: 10956044
    Abstract: An integrated circuit device includes a memory controller coupleable to a memory. The memory controller to schedule memory accesses to regions of the memory based on memory timing parameters specific to the regions. A method includes receiving a memory access request at a memory device. The method further includes accessing, from a timing data store of the memory device, data representing a memory timing parameter specific to a region of the memory cell circuitry targeted by the memory access request. The method also includes scheduling, at the memory controller, the memory access request based on the data.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: March 23, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Yi Xu, Nuwan S. Jayasena, Yuan Xie
  • Taint protection during speculative execution
    Patent number: 10956157
    Abstract: A subset of a set of architectural registers in a processing system is marked (or “tainted”) to indicate that speculative use of data in the subset of the architectural registers is constrained based on a taint handling policy. One or more speculation features supported by the processing system are disabled for the instruction so that the one or more speculation features cannot be used on data in the subset. In some cases, values of bits associated with the subset of architectural registers are modified to indicate that the subset is tainted. The taint handling policy can be indicated by values stored in a policy register. Taint markings are tracked in response to values stored in the tainted architectural registers being written to a memory or read from the memory.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: March 23, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: David Kaplan, Marius Evers
  • Retaining cache entries of a processor core during a powered-down state
    Patent number: 10956332
    Abstract: A processor core associated with a first cache initiates entry into a powered-down state. In response, information representing a set of entries of the first cache are stored in a retention region that receives a retention voltage while the processor core is in a powered-down state. Information indicating one or more invalidated entries of the set of entries is also stored in the retention region. In response to the processor core initiating exit from the powered-down state, entries of the first cache are restored using the stored information representing the entries and the stored information indicating the at least one invalidated entry.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: March 23, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: William L. Walker, Michael L. Golden, Marius Evers
  • System and method for storing cache location information for cache entry transfer
    Patent number: 10956339
    Abstract: A cache stores, along with data that is being transferred from a higher level cache to a lower level cache, information indicating the higher level cache location from which the data was transferred. Upon receiving a request for data that is stored at the location in the higher level cache, a cache controller stores the higher level cache location information in a status tag of the data. The cache controller then transfers the data with the status tag indicating the higher level cache location to a lower level cache. When the data is subsequently updated or evicted from the lower level cache, the cache controller reads the status tag location information and transfers the data back to the location in the higher level cache from which it was originally transferred.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: March 23, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Paul James Moyer
  • Processor support for hardware transactional memory
    Patent number: 10956163
    Abstract: A processing core of a plurality of processing cores is configured to execute a speculative region of code a single atomic memory transaction with respect one or more others of the plurality of processing cores. In response to determining an abort condition for issued one of the plurality of program instructions and in response to determining that the issued program instruction is not part of a mispredicted execution path, the processing core is configured to abort an attempt to execute the speculative region of code.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: March 23, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Jaewoong Chung, David S. Christie, Michael P. Hohmuth, Stephan Diestelhorst, Martin Pohlack, Luke Yen