Patents Assigned to ADVANCED MICRO DEVICES (AMD)
  • Near-memory data reduction
    Patent number: 11099788
    Abstract: An approach is provided for implementing near-memory data reduction during store operations to off-chip or off-die memory. A Near-Memory Reduction (NMR) unit provides near-memory data reduction during write operations to a specified address range. The NMR unit is configured with a range of addresses to be reduced and when a store operation specifies an address within the range of addresses, the NRM unit performs data reduction by adding the data value specified by the store operation to an accumulated reduction result. According to an embodiment, the NRM unit maintains a count of the number of updates to the accumulated reduction result that are used to determine when data reduction has been completed.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: August 24, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Nuwan Jayasena, Shaizeen Aga
  • Pre-discharged bypass flip-flop circuit
    Patent number: 11095274
    Abstract: A pre-discharged edge-triggered flip-flop, in which internal nodes determinative of an output signal are discharged to VSS prior to an evaluation phase of a clock signal, is provided to enable improved clock-to-output response times when provided with a rising edge of a clock pulse. In operation, during a pre-discharge phase of the clock signal, multiple internal nodes of a differential master latch circuit of the flip-flop are discharged to VSS. In response to a rising edge of the clock signal signaling the beginning of an evaluation phase, one of the internal nodes (selected depending on the logical value of an input signal to the flip-flop) is charged to VDD while other of the internal nodes remain at VSS. A single clock signal inverter is disposed between the input clock signal and a multiplexer providing the output data signal.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: August 17, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Nur Mohammad Baksh, Michael Q. Co
  • Matrix multiplier with submatrix sequencing
    Patent number: 11093580
    Abstract: A processor sequences the application of submatrices at a matrix multiplier to reduce the number of input changes at an input register of the matrix multiplier. The matrix multiplier is configured to perform a matrix multiplication for a relatively small matrix. To multiply two larger matrices the GPU decomposes the larger matrices into smaller submatrices and stores the submatrices at input registers of the matrix multiplier in a sequence, thereby calculating each column of a result matrix. The GPU sequences the storage of the submatrices at the input registers to maintain input data at one of the input registers over multiple calculation cycles of the matrix multiplier thereby reducing power consumption at the GPU.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: August 17, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Maxim V. Kazakov, Jian Mao
  • Deliberate conditional poison training for generative models
    Patent number: 11087170
    Abstract: A generator for generating artificial data, and training for the same. Data corresponding to a first label is altered within a reference labeled data set. A discriminator is trained based on the reference labeled data set to create a selectively poisoned discriminator. A generator is trained based on the selectively poisoned discriminator to create a selectively poisoned generator. The selectively poisoned generator is tested for the first label and tested for the second label to determine whether the generator is sufficiently poisoned for the first label and sufficiently accurate for the second label. If it is not, the generator is retrained based on the data set including the further altered data. The generator includes a first ANN to input first information and output a set of artificial data that is classifiable using a first label and not classifiable using a second label of the set of labeled data.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: August 10, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Nicholas Malaya
  • Data transfer acceleration
    Patent number: 11086809
    Abstract: Data transfer acceleration includes receiving, by a data transfer accelerator in a first node of a plurality of nodes, from a second node of the plurality of nodes, a request for data in a second state, wherein the second node stores an instance of the data in a first state; generating a message including one or more operations to transform the data from the first state to the second state; and sending the message to the second node in response to the request.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: August 10, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Anthony Gutierrez
  • Platform power manager for rack level power and thermal constraints
    Patent number: 11073888
    Abstract: Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: July 27, 2021
    Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Indrani Paul, Sriram Sambamurthy, Larry David Hewitt, Kevin M. Lepak, Samuel D. Naffziger, Adam Neil Calder Clark, Aaron Joseph Grenat, Steven Frederick Liepe, Sandhya Shyamasundar, Wonje Choi, Dana Glenn Lewis, Leonardo de Paula Rosa Piga
  • Automatic part testing
    Patent number: 11068368
    Abstract: Automatic part testing includes: booting a part under testing into a first operating environment; executing, via the first operating environment, one or more test patterns on the part; performing a comparison between one or more observed characteristics associated with the one or more test patterns and one or more expected characteristics; and modifying one or more operational parameters of a central processing unit of the part based on the comparison.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: July 20, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Amitabh Mehra, Anil Harwani, William R. Alverson, Grant E. Ley, Jerry A. Ahrens, Mustansir M. Pratapgarhwala, Scott E. Swanstrom
  • Dynamic configuration of inter-chip and on-chip networks in cloud computing system
    Patent number: 11064019
    Abstract: A server includes a plurality of nodes that are connected by a network that includes an on-chip network or an inter-chip network that connects the nodes. The server also includes a controller to configure the network based on relative priorities of workloads that are executing on the nodes. Configuring the network can include allocating buffers to virtual channels supported by the network based on the relative priorities of the workloads associated with the virtual channels, configuring routing tables that route the packets over the network based on the relative priorities of the workloads that generate the packets, or modifying arbitration weights to favor granting access to the virtual channels to packets generated by higher priority workloads.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: July 13, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Sergey Blagodurov
  • Setting durations for which data is stored in a non-volatile memory based on data types
    Patent number: 11061583
    Abstract: An electronic device includes a non-volatile memory and a controller. The controller receives data to be written to the non-volatile memory and determines a type of the data. Based on the type of the data, the controller selects a given duration of the data from among multiple durations of the data in the non-volatile memory. The controller sets values of one or more parameters for writing the data to the non-volatile memory based on the given duration. The controller writes the data to the non-volatile memory using the values of the one or more write parameters.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: July 13, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Andrew G. Kegel, Steven E. Raasch
  • Method and apparatus for directing application requests for rendering
    Patent number: 11055806
    Abstract: A method and system for directing image rendering, implemented in a computer system including a plurality of processors includes determining one or more processors in the system on which to execute one or more commands. A graphics processing unit (GPU) control application program interface (API) determines one or more processors in the system on which to execute one or more commands. A signal is transmitted to each of the one or more processors indicating which of the one or more commands are to be executed by that processor. The one or more processors execute their respective command. A request is transmitted to each of the one or more processors to transfer information to one another once processing is complete, and an image is rendered based upon the processed information by at least one processor and the received transferred information from at least another processor.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: July 6, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Gregory A. Grebe, Jonathan Lawrence Campbell, Layla A. Mah
  • Branch target buffer with early return prediction
    Patent number: 11055098
    Abstract: A processor includes a branch target buffer (BTB) having a plurality of entries whereby each entry corresponds to an associated instruction pointer value that is predicted to be a branch instruction. Each BTB entry stores a predicted branch target address for the branch instruction, and further stores information indicating whether the next branch in the block of instructions associated with the predicted branch target address is predicted to be a return instruction. In response to the BTB indicating that the next branch is predicted to be a return instruction, the processor initiates an access to a return stack that stores the return address for the predicted return instruction. By initiating access to the return stack responsive to the return prediction stored at the BTB, the processor reduces the delay in identifying the return address, thereby improving processing efficiency.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: July 6, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Aparna Thyagarajan, Marius Evers, Arunachalam Annamalai
  • Shader merge for reduced divergence
    Patent number: 11055895
    Abstract: Described herein are techniques for reducing control flow divergence. The method includes identifying two or more shader programs having commonalities, generating a merged shader program that implements functionality of the identified two or more shader programs, wherein the functionality implemented includes a first execution option for a first shader program of the two or more shader programs and a second execution option for a second shader program of the two or more shader programs, modifying shader programs that call the first shader program to instead call the merged shader program and select the first execution option, modifying shader programs that call the second shader program to instead call the merged shader program and select the second execution option.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: July 6, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: David Ronald Oldcorn
  • Circuit board with phase change material
    Patent number: 11049794
    Abstract: Various circuit board embodiments are disclosed. In one aspect, an apparatus is provided that includes a circuit board and a first phase change material pocket positioned on or in the circuit board and contacting a surface of the circuit board.
    Type: Grant
    Filed: March 1, 2014
    Date of Patent: June 29, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Manish Arora, Nuwan Jayasena
  • Tracking stores and loads by bypassing load store units
    Patent number: 11048506
    Abstract: A system and method for tracking stores and loads to reduce load latency when forming the same memory address by bypassing a load store unit within an execution unit is disclosed. Store-load pairs which have a strong history of store-to-load forwarding are identified. Once identified, the load is memory renamed to the register stored by the store. The memory dependency predictor may also be used to detect loads that are dependent on a store but cannot be renamed. In such a configuration, the dependence is signaled to the load store unit and the load store unit uses the information to issue the load after the identified store has its physical address.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: June 29, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Krishnan V. Ramani, Kai Troester, Frank C. Galloway, David N. Suggs, Michael D. Achenbach, Betty Ann McDaniel, Marius Evers
  • Providing interrupts from an input-output memory management unit to guest operating systems
    Patent number: 11042495
    Abstract: An electronic device includes a processor that executes a guest operating system; a memory having a guest portion that is reserved for storing data and information to be accessed by the guest operating system; and an input-output memory management unit (IOMMU). The IOMMU performs operations for signaling an interrupt to the guest operating system. For these operations, the IOMMU acquires, from an entry in an interrupt remapping table associated with the guest operating system, a location in a virtual advanced programmable interrupt controller (APIC) backing page for the guest operating system in the guest portion of the memory. The IOMMU then writes information about the interrupt to the location in the virtual APIC backing page. The IOMMU next communicates an indication of the interrupt to the guest operating system.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: June 22, 2021
    Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Maggie Chan, Philip Ng, Paul Blinzer
  • Targeted per-line operations for remote scope promotion
    Patent number: 11042484
    Abstract: A processing system includes one or more first caches and one or more first lock tables associated with the one or more first caches. The processing system also includes one or more processing units that each include a plurality of compute units for concurrently executing work-groups of work items, a plurality of second caches associated with the plurality of compute units and configured in a hierarchy with the one or more first caches, and a plurality of second lock tables associated with the plurality of second caches. The first and second lock tables indicate locking states of addresses of cache lines in the corresponding first and second caches on a per-line basis.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: June 22, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Johnathan R. Alsop, Bradford Beckmann
  • Energy efficient adaptive data encoding method and circuit
    Patent number: 11038526
    Abstract: Various energy efficient data encoding schemes and computing devices are disclosed. In one aspect, a method of transmitting data from a transmitter to a receiver connected by plural wires is provided. The method includes sending from the transmitter on at least one but not all of the wires a first wave form that has first and second signal transitions. The receiver receives the first waveform and measures a first duration between the first and second signal transitions using a locally generated clock signal not received from the transmitter. The first duration is indicative of a first particular data value.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: June 15, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Greg Sadowski, John Kalamatianos
  • Store-to-load forwarding
    Patent number: 11036505
    Abstract: An arithmetic unit performs store-to-load forwarding based on predicted dependencies between store instructions and load instructions. In some embodiments, the arithmetic unit maintains a table of store instructions that are awaiting movement to a load/store unit of the instruction pipeline. In response to receiving a load instruction that is predicted to be dependent on a store instruction stored at the table, the arithmetic unit causes the data associated with the store instruction to be placed into the physical register targeted by the load instruction. In some embodiments, the arithmetic unit performs the forwarding by mapping the physical register targeted by the load instruction to the physical register where the data associated with the store instruction is located.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: June 15, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Gregory W. Smaus, Francesco Spadini, Matthew A. Rafacz, Michael Achenbach, Christopher J. Burke, Emil Talpes, Matthew M. Crum
  • Protecting host memory from access by untrusted accelerators
    Patent number: 11030117
    Abstract: A host processor receives an address translation request from an accelerator, which may be trusted or un-trusted. The address translation request includes a virtual address in a virtual address space that is shared by the host processor and the accelerator. The host processor encrypts a physical address in a host memory indicated by the virtual address in response to the accelerator being permitted to access the physical address. The host processor then provides the encrypted physical address to the accelerator. The accelerator provides memory access requests including the encrypted physical address to the host processor, which decrypts the physical address and selectively accesses a location in the host memory indicated by the decrypted physical address depending upon whether the accelerator is permitted to access the location indicated by the decrypted physical address.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: June 8, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Nuwan Jayasena, Brandon K. Potter, Andrew G. Kegel
  • Virtual space memory bandwidth reduction
    Patent number: 11030095
    Abstract: A processing system includes a central processing unit (CPU) and a graphics processing unit (GPU) that has a plurality of compute units. The GPU receives an image from the CPU and determines a total result area in a virtual-matrix-multiplication space of a virtual matrix-multiplication output matrix based on convolutional parameters associated with the image in an image space. The GPU partitions the total result area of the virtual matrix-multiplication output matrix into a plurality of virtual segments. The GPU allocates convolution operations to the plurality of compute units based on each virtual segment of the plurality of virtual segments.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: June 8, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Swapnil Sakharshete, Samuel Lawrence Wasmundt