Patents Assigned to ADVANCED MICRO DEVICES (AMD)
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Publication number: 20170004080Abstract: Methods, devices, and systems for managing performance of a processor having multiple compute units. An effective number of the multiple compute units may be determined to designate as having priority. On a condition that the effective number is nonzero, the effective number of the multiple compute units may each be designated as a priority compute unit. Priority compute units may have access to a shared cache whereas non-priority compute units may not. Workgroups may be preferentially dispatched to priority compute units. Memory access requests from priority compute units may be served ahead of requests from non-priority compute units.Type: ApplicationFiled: June 30, 2015Publication date: January 5, 2017Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Zhe Wang, Sooraj Puthoor, Bradford M. Beckmann
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Patent number: 9535627Abstract: A system, method and computer-readable storage device for accessing heterogeneous memory system, are provided. A memory controller schedules access of a command to a memory region in a set of memory regions based on an access priority associated with the command and where the set of memory regions have corresponding access latencies. The memory controller also defers access of the command to the set of memory regions using at least two queues and the access priority.Type: GrantFiled: October 2, 2013Date of Patent: January 3, 2017Assignee: ADVANCED MICRO DEVICES, INC.Inventors: David A. Roberts, Michael Ignatowski
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Patent number: 9535849Abstract: An IOMMU for controlling requests by an I/O device to a system memory of a computer system includes control logic and a cache memory. The control logic may translate an address received in a request from the I/O device. If the request includes a transaction layer protocol (TLP) packet with a process address space identifier (PASID) prefix, the control logic may perform a two-level guest translation. Accordingly, the control logic may access a set of guest page tables to translate the address received in the request. A pointer in a last guest page table points to a first table in a set of nested page tables. The control logic may use the pointer in a last guest page table to access the set of nested page tables to obtain a system physical address (SPA) that corresponds to a physical page in the system memory. The cache memory stores completed translations.Type: GrantFiled: July 24, 2009Date of Patent: January 3, 2017Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Andrew G. Kegel, Mark D. Hummel, Stephen D. Glaser
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Publication number: 20160378791Abstract: A method and apparatus for performing a top-down Breadth-First Search (BFS) includes performing a first determination whether to convert to a bottom-up BFS. A second determination is performed whether to convert to the bottom-up BFS, based upon the first determination being positive. The bottom-up BFS is performed, based upon the first determination and the second determination being positive. A third determination is made whether to convert from the bottom-up BFS to the top-down BFS, based upon the third determination being positive.Type: ApplicationFiled: June 24, 2015Publication date: December 29, 2016Applicant: ADVANCED MICRO DEVICES, INC.Inventor: Mayank Daga
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Patent number: 9529719Abstract: Apparatus and method embodiments for dynamically allocating cache space in a multi-threaded execution environment are disclosed. In some embodiments, a processor includes a cache shared by each of a plurality of processor cores and/or each of a plurality of threads executing on the processor. The processor further includes a cache allocation circuit configured to dynamically allocate space in the cache provided to each of the plurality of processor cores based on their respective usage patterns. The cache allocation unit may track cache usage by each of the processor cores/threads using subsets of usage bits and counters configured to update states of the usage bits. The cache allocation circuit may track the usage of cache space by the processor cores/threads and may allocate more space to those that exhibit more usage of the cache.Type: GrantFiled: August 5, 2012Date of Patent: December 27, 2016Assignee: ADVANCED MICRO DEVICES, INC.Inventor: William L. Walker
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Patent number: 9519483Abstract: A method and apparatus are described for generating flags in response to processing data during an execution pipeline cycle of a processor. The processor may include a multiplexer configured to generate valid bits for received data according to a designated data size, and a logic unit configured to control the generation of flags based on a shift or rotate operation command, the designated data size and information indicating how many bytes and bits to rotate or shift the data by. A carry flag may be used to extend the amount of bits supported by shift and rotate operations. A sign flag may be used to indicate whether a result is a positive or negative number. An overflow flag may be used to indicate that a data overflow exists, whereby there are not a sufficient number of bits to store the data.Type: GrantFiled: December 22, 2011Date of Patent: December 13, 2016Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Srikanth Arekapudi, Saurabh Gupta
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Patent number: 9508408Abstract: A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal.Type: GrantFiled: April 2, 2014Date of Patent: November 29, 2016Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Ming-Ju Edward Lee, Shadi M. Barakat, Warren Fritz Kruger, Xiaoling Xu, Toan Duc Pham, Aaron John Nygren
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Publication number: 20160342185Abstract: A processor system includes first and second regulators for regulating an adjusted supply voltage. The first and second regulators generate a plurality of control signals to regulate an adjusted power supply voltage and that generate a charge when a droop level falls below a droop threshold value by implementing first and second control loops. A supply adjustment block with the two regulators and control loops are provided for each processor core allowing different cores to have different regulated supply levels all based on one common supply. One regulator is a global regulator while another is a local regulator found in each of the processing tiles. Processing tiles are grouped into two groups wherein one group includes tiles that may powered down to save power. Voltage rails of the two groups are selectively connected to equalize voltage levels when both groups are powered on and operating.Type: ApplicationFiled: October 21, 2015Publication date: November 24, 2016Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Miguel Rodriguez, Stephen Victor Kosonocky
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Publication number: 20160341793Abstract: In one form, a scan flip-flop includes a clock gating cell and a dedicated clock flip-flop. The clock gating cell provides an input clock input signal as a scan clock signal when a scan shift enable signal is active, and provides the input clock signal as a data clock signal when the scan shift enable signal is inactive. The dedicated clock flip-flop stores a data input signal and provides the data input signal, so stored, as a data output signal in response to transitions of the data clock signal, and stores a scan data input signal and provides the scan data input signal, so stored, as the data output signal in response to transitions of the scan clock signal. The clock gating cell may further provide the input clock signal as the data clock signal when both a scan shift enable signal is inactive and a data enable signal is active.Type: ApplicationFiled: May 19, 2015Publication date: November 24, 2016Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Daniel W. Bailey, Abhishek Sharma, Michael Q. Co
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Patent number: 9489173Abstract: A computing device with a queue stored in a memory of the computing device is described. The queue may be relocated and/or resized in the memory using a queue address, a queue size, a head pointer, and/or a tail pointer associated with the queue. During operation, a processor, at the request of a software entity, updates one or more values associated with the queue to relocate and/or resize the queue. In response, a write mechanism performs one or more operations to enable the use of the relocated and/or resized queue. In addition, when the queue is relocated, the processor, at the request of the software entity, performs one or more operations to process remaining valid entries in an original location of the queue.Type: GrantFiled: June 4, 2014Date of Patent: November 8, 2016Assignee: ADVANCED MICRO DEVICES, INC.Inventor: Andrew G. Kegel
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Patent number: 9484113Abstract: A memory read operation is directed at a group of semiconductor devices from which a first semiconductor device has been removed. An error in data for the memory read operation is detected based on error-correction coding (ECC). The error is caused at least in part by the first semiconductor device having been removed. ECC is used to determine corrected data for the memory read operation.Type: GrantFiled: April 15, 2014Date of Patent: November 1, 2016Assignee: ADVANCED MICRO DEVICES, INC.Inventor: David A. Roberts
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Patent number: 9477289Abstract: A system has a plurality of electronic components including a memory, a PHY coupled to the memory, and one or more other electronic components. Power consumed by the PHY is estimated during operation of the system. Estimating the power consumed by the PHY includes modeling the power consumed by the PHY as a linear function with respect to memory bandwidth. Available power for the PHY is determined based at least in part on the estimated power consumed by the PHY. At least a portion of the available power for the PHY is allocated to at least one of the one or more other components.Type: GrantFiled: March 25, 2014Date of Patent: October 25, 2016Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Ashish Jain, Alexander J. Branover, Guhan Krishnan
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Patent number: 9479449Abstract: A method of computing is performed in a first processing node of a plurality of processing nodes of multiple types with distinct processing capabilities. The method includes, in response to a command, partitioning data associated with the command among the plurality of processing nodes. The data is partitioned based at least in part on the distinct processing capabilities of the multiple types of processing nodes.Type: GrantFiled: June 3, 2013Date of Patent: October 25, 2016Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Mauricio Breternitz, Gary Frost
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Patent number: 9472299Abstract: A memory cell is read by measuring a parameter associated with the memory cell with a first resolution to determine a value stored in the memory cell. The parameter is also measured with a second resolution that is finer than the first resolution. The memory cell is reprogrammed to mitigate an offset between the parameter as measured with the second resolution and the parameter as measured with the first resolution.Type: GrantFiled: April 21, 2014Date of Patent: October 18, 2016Assignee: ADVANCED MICRO DEVICES, INC.Inventors: David A. Roberts, Michael Ignatowski
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Patent number: 9471799Abstract: A system and method are disclosed for securely receiving data from an input device coupled to a computing system. The system includes an interface configured to receive data from an input device, a coprocessor, and a host computer, wherein the host computer includes an input handler and a host processor. The host processor is configured to execute code in a normal mode and in a privileged mode. The host processor switches from the normal mode to the secure mode upon data being available from the interface while the host computer is in a secure input mode. The input handler receives the data from the interface and sends the received data to the coprocessor responsive to receiving the data while operating in the secure mode.Type: GrantFiled: September 22, 2014Date of Patent: October 18, 2016Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Joshua S. Schiffman, David A. Kaplan
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Patent number: 9471130Abstract: The described embodiments include a computing device with an entity (a processor, a processor core, etc.) and a controller. In these embodiments, the controller, using an idle duration history, predicts a duration of a next idle period for the entity. Based on the predicted duration of the next idle period, the controller configures the entity to operate in a corresponding idle state.Type: GrantFiled: October 25, 2013Date of Patent: October 18, 2016Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Manish Arora, Nuwan S. Jayasena, Michael J. Schulte
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Publication number: 20160291678Abstract: In one form, power consumed in transmitting data over a bus interconnect is reduced. The power is reduced by configuring a buffer that is used to store data to be transmitted over the bus interconnect as a two-dimensional (2D) buffer array having a plurality of rows and columns. The data stored in the 2D buffer array is then analyzed to determine a mode of transmitting the data that uses a least amount of power. The determined mode is used to transmit the data over the bus interconnect.Type: ApplicationFiled: March 30, 2015Publication date: October 6, 2016Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Greg Sadowski, John Kalamatianos
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Patent number: 9448933Abstract: In the described embodiments, a processor core (e.g., a GPU core) receives a section of program code to be executed in a transaction from another entity in a computing device. The processor core sends the section of program code to one or more compute units in the processor core to be executed in a first transaction and concurrently executed in a second transaction, thereby creating a “redundant transaction pair.” When the first transaction and the second transaction are completed, the processor core compares a read-set of the first transaction to a read-set of the second transaction and compares a write-set of the first transaction to a write-set of the second transaction. When the read-sets and the write-sets match and no transactional error condition has occurred, the processor core allows results from the first transaction to be committed to an architectural state of the computing device.Type: GrantFiled: August 29, 2013Date of Patent: September 20, 2016Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Sudhanva Gurumurthi, Vilas Sridharan
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Patent number: 9442557Abstract: The described embodiments include a computing device with one or more entities (processor cores, processors, etc.). In some embodiments, during operation, a thermal power management unit in the computing device uses a linear prediction to compute a predicted duration of a next idle period for an entity based on the duration of one or more previous idle periods for the entity. Based on the predicted duration of the next idle period, the thermal power management unit configures the entity to operate in a corresponding idle state.Type: GrantFiled: November 8, 2013Date of Patent: September 13, 2016Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Manish Arora, Nuwan S. Jayasena, Yasuko Eckert, Madhu Saravana Sibi Govindan, William L. Bircher, Michael J. Schulte, Srilatha Manne
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Publication number: 20160261869Abstract: A method of video encoding is disclosed which is content adaptive. The encoding method is automatically adjusted to optimize the encoding, the adjusting depending on the content of the pictures being encoded. A system for implementing the method and a non-transitory computer-readable storage medium for storing instructions of the method are also disclosed.Type: ApplicationFiled: March 4, 2015Publication date: September 8, 2016Applicants: ATI Technologies ULC, ADVANCED MICRO DEVICES, INC.Inventors: Khaled Mammou, Ihab M. A. Amer, Oleksandr O. Bobrovnik, Vladyslav S. Zakharchenko
