Patents Assigned to ADVANCED MICRO DEVICES (AMD)
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Patent number: 10324760Abstract: The described embodiments include a computing device that has two or more levels of memory, each level of memory having different performance characteristics. During operation, the computing device receives a request to lease an available block of memory in a specified level of memory for storing an object. When a block of memory is available for leasing in the specified level of memory, the computing device stores the object in the block of memory in the specified level of memory. The computing device also commences the lease for the block of memory by setting an indicator for the block of memory to indicate that the block of memory is leased. During the lease (i.e., until the lease is terminated), the object is kept in the block of memory.Type: GrantFiled: April 29, 2016Date of Patent: June 18, 2019Assignee: ADVANCED MICRO DEVICES, INC.Inventor: Mitesh Meswani
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Publication number: 20190179798Abstract: A method and apparatus for scheduling instructions of a shader program for a graphics processing unit (GPU) with a fixed number of registers. The method and apparatus include computing, via a processing unit (PU), a liveness-based register usage across all basic blocks in the shader program, computing, via the PU, the range of numbers of waves of a plurality of registers for the shader program, assessing the impact of available post-register allocation optimizations, computing, via the PU, the scoring data based on number of waves of the plurality of registers, and computing, via the PU, the number of waves for execution for the plurality of registers.Type: ApplicationFiled: February 4, 2019Publication date: June 13, 2019Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Robert A. Gottlieb, Christopher L. Reeve, Michael John Bedy
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Patent number: 10310981Abstract: A method and apparatus for performing memory prefetching includes determining whether to initiate prefetching. Upon a determination to initiate prefetching, a first memory row is determined as a suitable prefetch candidate, and it is determined whether a particular set of one or more cachelines of the first memory row is to be prefetched.Type: GrantFiled: September 19, 2016Date of Patent: June 4, 2019Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Yasuko Eckert, Nuwan Jayasena, Reena Panda, Onur Kayiran, Michael W. Boyer
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Patent number: 10296378Abstract: A system and methods embodying some aspects of the present embodiments for efficient load balancing using predication flags are provided. The load balancing system includes a first processing unit, a second processing unit, and a shared queue. The first processing unit is in communication with a first queue. The second processing unit is in communication with a second queue. The first and second queues are each configured to hold a packet. The shared queue is configured to maintain a work assignment, wherein the work assignment is to be processed by either the first or second processing unit.Type: GrantFiled: January 31, 2017Date of Patent: May 21, 2019Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Vinod Tipparaju, Lee Howes, Thomas Scogland
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Publication number: 20190146799Abstract: A method, system, and computer program product synchronize a group of workitems executing an instruction stream on a processor. The processor is yielded by a first workitem responsive to a synchronization instruction in the instruction stream. A first one of a plurality of program counters is updated to point to a next instruction following the synchronization instruction in the instruction stream to be executed by the first workitem. A second workitem is run on the processor after the yielding.Type: ApplicationFiled: November 29, 2018Publication date: May 16, 2019Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Lee W. HOWES, Benedict R. GASTER, Michael C. HOUSTON
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Patent number: 10283437Abstract: Methods, a computer readable medium, and an apparatus are provided. A method includes and the computer readable medium is configured for decomposing an overall pattern into a first mask pattern that includes a power rail base pattern and into a second mask pattern, and generating on the second mask pattern a power rail insert pattern that is at least partially aligned with the power rail base pattern of the first mask pattern. The apparatus is produced by photolithography using photolithographic masks generated by the method.Type: GrantFiled: November 27, 2012Date of Patent: May 7, 2019Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Richard T. Schultz, Omid Rowhani, Charles P. Tung
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Patent number: 10282292Abstract: Cluster manager functional blocks perform operations for migrating pages in portions in corresponding migration clusters. During operation, each cluster manager keeps an access record that includes information indicating accesses of pages in the portions in the corresponding migration cluster. Based on the access record and one or more migration policies, each cluster manager migrates pages between the portions in the corresponding migration cluster.Type: GrantFiled: October 17, 2016Date of Patent: May 7, 2019Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Andreas Prodromou, Mitesh R. Meswani, Arkaprava Basu, Nuwan S. Jayasena, Gabriel H. Loh
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Patent number: 10261916Abstract: The described embodiments include a computing device with two or more translation lookaside buffers (TLB). During operation, the computing device updates an entry in the TLB based on a virtual address to physical address translation and metadata from a page table entry that were acquired during a page table walk. The computing device then computes, based on a lease length expression, a lease length for the entry in the TLB. Next, the computing device sets, for the entry in the TLB, a lease value to the lease length, wherein the lease value represents a time until a lease for the entry in the TLB expires, wherein the entry in the TLB is invalid when the associated lease has expired. The computing device then uses the lease value to control operations that are allowed to be performed using information from the entry in the TLB.Type: GrantFiled: November 25, 2016Date of Patent: April 16, 2019Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Amro Awad, Sergey Blagodurov, Arkaprava Basu, Mark H. Oskin, Gabriel H. Loh, Andrew G. Kegel, David S. Christie, Kevin J. McGrath
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Patent number: 10248315Abstract: Described are aggregation devices and methods for interconnecting server nodes. The aggregation device can include an input region, an output region, and a memory switch. The input region includes a plurality of input ports. The memory switch has a shared through silicon via (TSV) memory coupled to the input ports for temporarily storing data received at the input ports from a plurality of source devices. The output region includes a plurality of output ports coupled to the TSV memory. The output ports provide the data to a plurality of destination devices. A memory allocation system coordinates a transfer of the data from the source devices to the TSV memory. The output ports receive and process the data from the TSV memory independently of a communication from the input ports.Type: GrantFiled: September 14, 2015Date of Patent: April 2, 2019Assignee: ADVANCED MICRO DEVICES, INC.Inventors: David E. Mayhew, Mark D. Hummel, Michael J. Osborn
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Patent number: 10241931Abstract: A table walker receives, from a requesting entity, a request to translate a first address into a second address associated with a page of memory. During a corresponding table walk, when a lock indicator in an entry in a reverse map table (RMT) for the page is set to mark the entry in the RMT as locked, the table walker halts processing the request and performs a remedial action. In addition, when the request is associated with a write access of the page and an immutable indicator in the entry in the RMT is set to mark the page as immutable, the table walker halts processing the request and performs the remedial action. Otherwise, when the entry in the RMT is not locked and the page is not marked as immutable for a write access, the table walker continues processing the request.Type: GrantFiled: January 27, 2017Date of Patent: March 26, 2019Assignee: ADVANCED MICRO DEVICES, INC.Inventors: David A. Kaplan, Jeremy W. Powell, Thomas R. Woller
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Patent number: 10217280Abstract: Techniques for removing reset indices from, and identifying primitives in, an index stream that defines a set of primitives to be rendered, are disclosed. The index stream may be specified by an application program executing on the central processing unit. The technique involves classifying the primitive topology for the index stream as either requiring an offset-based technique or requiring a non-offset-based technique. This classification is done by determining whether, according to the primitive topology, each subsequent index can form a primitive with prior indices (e.g., line strip, triangle strip). If each subsequent index can form a primitive with prior indices, then the technique used is the non-offset-based technique. If each subsequent index does not form a primitive with prior indices, but instead at least two indices are required to form a new primitive (e.g., line list, triangle list), then the technique used is the offset-based technique.Type: GrantFiled: November 17, 2016Date of Patent: February 26, 2019Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Saad Arrabi, Mangesh P. Nijasure, Todd Martin
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Patent number: 10198358Abstract: Apparatuses, computer readable mediums, and methods of processor unit testing using cache resident testing are disclosed. The method may include loading a test program in a cache on a chip comprising one or more processor units. The method may include the one or more processor units executing the test program to generate one or more results. The method may include redirecting a first memory reference to the cache, wherein the first memory reference is generated during the execution of the test program. The method may include determining whether the one or more generated results match one or more test results. The method may include redirecting a memory request to a memory location resident in the cache if the memory request includes a memory location not resident in the cache. The method may include redirecting a memory request to the cache if the memory request is not directed to the cache.Type: GrantFiled: April 2, 2014Date of Patent: February 5, 2019Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Angel E. Socarras, Kostantinos Danny Christidis, Curtis Alan Gilgan, Alexander Fuad Ashkar
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Patent number: 10198259Abstract: A method and apparatus for scheduling instructions of a shader program for a graphics processing unit (GPU) with a fixed number of registers. The method and apparatus include computing, via a processing unit (PU), a liveness-based register usage across all basic blocks in the shader program, computing, via the PU, the range of numbers of waves of a plurality of registers for the shader program, assessing the impact of available post-register allocation optimizations, computing, via the PU, the scoring data based on number of waves of the plurality of registers, and computing, via the PU, the number of waves for execution for the plurality of registers.Type: GrantFiled: June 23, 2016Date of Patent: February 5, 2019Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Robert A. Gottlieb, Christopher L. Reeve, Michael John Bedy
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Patent number: 10198789Abstract: Techniques for allowing cache access returns out of order are disclosed. A return ordering queue exists for each of several cache access types and stores outstanding cache accesses in the order in which those accesses were made. When a cache access request for a particular type is at the head of the return ordering queue for that type and the cache access is available for return to the wavefront that made that access, the cache system returns the cache access to the wavefront. Thus, cache accesses can be returned out of order with respect to cache accesses of different types. Allowing out-of-order returns can help to improve latency, for example in the situation where a relatively low-latency access type (e.g., a read) is issued after a relatively high-latency access type (e.g., a texture sampler operation).Type: GrantFiled: December 13, 2016Date of Patent: February 5, 2019Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Daniel Schneider, Fataneh Ghodrat
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Patent number: 10199732Abstract: An apparatus comprising at least one antenna for transmission and/or reception of circularly polarized electromagnetic radiation. The antenna includes a radiating element, a static element, and a single feed line. The single feed line is coupled between the radiating element and a circuit that drives the antenna. The radiating element has a non-symmetrical outer perimeter shape. The radiating element may include an aperture. The antenna may further include a ground element and a supplemental ground feed structure, the supplemental ground feed structure located between the radiating element and the ground element and the radiating element located between the supplemental ground feed structure and the static element.Type: GrantFiled: December 30, 2014Date of Patent: February 5, 2019Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Stevan Preradovic, Bo Yang, Natalino Camilleri
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Publication number: 20190013051Abstract: A system, method, and computer program product are provided for a memory device system. One or more memory dies and at least one logic die are disposed in a package and communicatively coupled. The logic die comprises a processing device configurable to manage virtual memory and operate in an operating mode. The operating mode is selected from a set of operating modes comprising a slave operating mode and a host operating mode.Type: ApplicationFiled: September 12, 2018Publication date: January 10, 2019Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Nuwan S. Jayasena, Gabriel H. Loh, Bradford M. Beckmann, James M. O'Connor, Lisa R. Hsu
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Patent number: 10170994Abstract: The described embodiments include an apparatus that controls voltages for an integrated circuit chip having a set of circuits. The apparatus includes a switching voltage regulator separate from the integrated circuit chip and two or more low dropout (LDO) regulators fabricated on the integrated circuit chip. During operation, the switching voltage regulator provides an output voltage that is received as an input voltage by each of the two or more LDO regulators, and each of the two or more LDO regulators provides a local output voltage, each local output voltage received as a local input voltage by a different subset of circuits in the set of circuits.Type: GrantFiled: August 22, 2017Date of Patent: January 1, 2019Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Thomas J. Gibney, Larry D. Hewitt, Daniel L. Bouvier
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Patent number: 10169244Abstract: The described embodiments perform a method for handling memory accesses by virtual machines in a computing device. The described embodiments include a reverse map table (RMT) and a separate guest accessed pages table (GAPT) for each virtual machine. The RMT has a plurality of entries, each entry including information for identifying a virtual machine that is permitted to access an associated page of data in a memory. Each GAPT has a record of pages being accessed by a corresponding virtual machine. During operation, a table walker receives a request from a given virtual machine to translate a guest physical address to a system physical address. The table walker checks at least one of the RMT and a corresponding GAPT to determine whether the given virtual machine has access to a corresponding page. If not, the table walker terminates the translating. Otherwise, the table walker completes the translating.Type: GrantFiled: July 29, 2016Date of Patent: January 1, 2019Assignee: ADVANCED MICRO DEVICES, INC.Inventors: David A. Kaplan, Jeremy W. Powell, Thomas R. Woller
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Patent number: 10158175Abstract: An apparatus comprising at least one antenna for transmission and/or reception of circularly polarized electromagnetic radiation. The antenna includes a radiating element and a single feed line. The single feed line is coupled between the radiating element and a circuit that drives the antenna. The radiating element has a non-symmetrical outer perimeter shape. The radiating element may include an aperture. The antenna may further include a ground element and a supplemental ground feed structure, the supplemental ground feed structure located between the radiating element and the ground element.Type: GrantFiled: December 30, 2014Date of Patent: December 18, 2018Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Stevan Preradovic, Bo Yang, Natalino Camilleri
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Publication number: 20180349057Abstract: Described herein is a method and system for directly accessing and transferring data between a first memory architecture and a second memory architecture associated with a graphics processing unit (GPU) by treating the first memory architecture, the second memory architecture and system memory as a single physical memory, where the first memory architecture is a non-volatile memory (NVM) and the second memory architecture is a local memory. Upon accessing a virtual address (VA) range by a processor, the requested content is paged in from the single physical memory and is then redirected by a virtual storage driver to the second memory architecture or the system memory, depending on which of the GPU or CPU triggered the access request. The memory transfer occurs without awareness of the application and the operating system.Type: ApplicationFiled: August 6, 2018Publication date: December 6, 2018Applicants: ATI Technologies ULC, ADVANCED MICRO DEVICES, INC.Inventors: Nima OSQUEIZADEH, Paul BLINZER