Abstract: Methods, devices, and systems for capturing an accuracy of an instruction executing on a processor. An instruction may be executed on the processor, and the accuracy of the instruction may be captured using a hardware counter circuit. The accuracy of the instruction may be captured by analyzing bits of at least one value of the instruction to determine a minimum or maximum precision datatype for representing the field, and determining whether to adjust a value of the hardware counter circuit accordingly. The representation may be output to a debugger or logfile for use by a developer, or may be output to a runtime or virtual machine to automatically adjust instruction precision or gating of portions of the processor datapath.

Abstract: An internal bus architecture and method is described. Embodiments include a system with multiple bus endpoints coupled to a bus. In addition, the bus endpoints are directly coupled to each other. Embodiments are usable with known bus protocols.

Abstract: The described embodiments include a computing device with a first entity and a second entity. In the computing device, a management controller dynamically sets a power-state limit for the first entity based on a performance coupling and a thermal coupling between the first entity and the second entity.

Abstract: In the described embodiments, entities in a computing device selectively write specified values to a lock variable in a local cache and one or more lower levels of a memory hierarchy to enable multiple entities to enable the concurrent execution of corresponding critical sections of program code that are protected by a same lock.

Abstract: The described embodiments include a system for executing a load using a first processor and a seond processor in a computer system. During operation, a load balancer executing on the first processor obtains one or more attributes of a load to be executed on the computer system. Next, the load balancer applies a set of configurable rules to the one or more attributes to select a processor from the first and second processors for executing the load. Finally, the system executes the load on the selected processor.

Abstract: A system and method are disclosed for managing memory interleaving patterns in a system with multiple memory devices. The system includes a processor configured to access multiple memory devices. The method includes receiving a first plurality of data blocks, and then storing the first plurality of data blocks using an interleaving pattern in which successive blocks of the first plurality of data blocks are stored in each of the memory devices. The method also includes receiving a second plurality of data blocks, and then storing successive blocks of the second plurality of data blocks in a first memory device of the multiple memory devices.

Abstract: The present invention relates to a substrate comprising a build-up and a solder resist layer disposed on the build-up. The solder resist layer has an upper surface facing away from the build-up. The solder resist layer has a plurality of grooves on its upper surface. The grooves of the solder resist layer can better eliminate or relieve the stress accumulated on large solder resist area induced by heat and/or material coefficient of thermal expansion mismatch of the substrate and thus can prevent and diminish warpage of the substrate or package.

Abstract: Apparatus and method embodiments for dynamically allocating cache space in a multi-threaded execution environment are disclosed. In some embodiments, a processor includes a cache shared by each of a plurality of processor cores and/or each of a plurality of threads executing on the processor. The processor further includes a cache allocation circuit configured to dynamically allocate space in the cache provided to each of the plurality of processor cores based on their respective usage patterns. The cache allocation unit may track cache usage by each of the processor cores/threads using subsets of usage bits and counters configured to update states of the usage bits. The cache allocation circuit may track the usage of cache space by the processor cores/threads and may allocate more space to those that exhibit more usage of the cache.

Abstract: A method and apparatus for reducing dynamic power consumption in a multi-thread content-addressable memory is described. The apparatus includes a first input configured to receive a first virtual address corresponding to a first thread, a second input configured to receive a second virtual address corresponding to a second thread, a register bank including a plurality of registers each configured to store a binary word mapped to one of a plurality of physical addresses, a first comparator bank including a first plurality of comparators each coupled to an associated register of the plurality of registers in a fully-associative configuration, and a second comparator bank including a second plurality of comparators each coupled to an associated register of the plurality of registers in a fully-associative configuration. An input virtual address to each comparator bank maintains its previous value for when a corresponding thread is not selected.

Abstract: Techniques to maintain gain flatness in the frequency response of a passband signal over a circuit chain. The techniques may be employed in the receive chain of a millimeter wave band wireless receiver, in the transmit chain of a millimeter wave band wireless transmitter, or in both the receive chain and the transmit chain of a millimeter wave band wireless transceiver. The techniques include mismatching the input and output impedance of a passive low pass filter used in the chain to peak the gain of the passband signal at or near the cutoff frequency (Fc) of the filter.

Abstract: An apparatus that includes three or more antennas and an integrated circuit selects antennas for use, i.e., for transmission and reception of electromagnetic radiation. The apparatus selects, at a first time, from the three or more antennas, two antennas having approximately the same feed line length so that the two antennas operate at the same phase and at a first angle. The apparatus selects, at a second time that is different than the first time, from the three or more antennas, two antennas having different feed line lengths so that the two antennas selected for use at the second time operate at different phases and at a second angle that is different than the first angle. In this manner the apparatus may change the pattern and/or shape of electromagnetic radiation transmitted by the apparatus by selecting for use particular antennas having different feed line lengths.

Abstract: The described embodiments include a computing device that performs operations for at least one of resizing or relocating a table in a memory in the computing device. In the described embodiments, the computing device includes at least one register storing a table base address indicating an original location of an original table in the memory and a table size indicating an original size of the original table in the memory. When relocating the original table, the computing device copies, using the table base address, some or all of the entries from the original table to a new table in the memory and then updates the table base address to indicate a location of the new table in the memory. When resizing the original table, the computing device updates the table size to indicate a new size.

Abstract: An apparatus for reducing interference and improving communication quality for RF communications over mm-wave frequency bands between wireless communications devices. In one embodiment, for example, the apparatus comprises a plurality of high-gain directional antenna elements each configured to maximally radiate in different directions relative to the apparatus. The apparatus also includes a RFIC chip electrically coupled to the plurality of antenna elements and configured to switch from driving any one of the directional antenna elements to driving another of the directional antenna elements thereby providing a multi-directional or near omni-directional radiation capability for a wireless communications device.

Abstract: A system has a plurality of functional modules including a first functional module and one or more other functional modules. The first functional module includes an embedded memory element and is configurable in a plurality of modes including a first mode and a second mode. When the first functional module is in the first mode, access to the embedded memory element is limited to the first functional module. At least one of the one or more other functional modules is provided with access to the embedded memory element based at least in part on the first functional module being in the second mode.

Abstract: The described embodiments comprise a selection mechanism that selects a resource from a set of resources in a computing device for performing an operation. In some embodiments, the selection mechanism performs a lookup in a table selected from a set of tables to identify a resource from the set of resources. When the resource is not available for performing the operation and until another resource is selected for performing the operation, the selection mechanism identifies a next resource in the table and selects the next resource for performing the operation when the next resource is available for performing the operation.

Abstract: A method, a system and a computer-readable medium for writing to a cache memory are provided. The method comprises maintaining a write count associated with a set, the set containing a memory block associated with a physical block address. A mapping from a logical address to the physical address of the block is also maintained. The method shifts the mapping based on the value of the write count and writes data to the block based on the mapping.

Abstract: A system for saving the architectural state of a processor is described. The system performs a save state operation, which involves, for each sector in a set of sectors of the architectural state, determining whether the architectural state for the sector has already been saved to a memory, and saving the architectural state for the sector to the memory when the architectural state for the sector has not already been saved to the memory. Each sector in the set of sectors comprises a different and separate portion of the architectural state of the processor. The system determines whether the architectural state for a given sector has already been saved to the memory by checking a needs-rinsing flag for the given sector. The needs-rinsing flag for the given sector is asserted upon modifying the given sector and cleared following the save state operation.

Abstract: A method, a device, and a non-transitory computer readable medium for performing memory management in a graphics processing unit are presented. Hints about the memory usage of an application are provided to a page manager. At least one runtime memory usage pattern of the application is sent to the page manager. Data is swapped into and out of a memory by analyzing the hints and the at least one runtime memory usage pattern.

Abstract: A method of enhancing performance of an application executing in a parallel processor and a system for executing the method are disclosed. A block size for input to the application is determined. Input is partitioned into blocks having the block size. Input within each block is sorted. The application is executed with the sorted input.

Abstract: Embodiments of a peripheral component are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors in one peripheral component can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols.