Patents Assigned to Advanced Micro Devices
  • DISTRIBUTION OF POWER GATING CONTROLS FOR HIERARCHICAL POWER DOMAINS
    Publication number: 20140298068
    Abstract: An integrated circuit device includes a first module disposed within a first power domain, a second module disposed in a second power domain that is a sub-domain of the first power domain, first power gating logic, and second power gating logic. The first power gating logic generates a first virtual power supply for the first module. The second power gating logic is powered by the first virtual power supply for generating a second virtual power supply for the second power domain.
    Type: Application
    Filed: April 1, 2013
    Publication date: October 2, 2014
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Stephen V. Kosonocky, Christopher Spence Oliver, Sudha Thiruvengadam, Carson D. Henrion
  • MULTIPLE HASH TABLE INDEXING
    Publication number: 20140297996
    Abstract: A processor includes storage elements to store a first and second value, as well as a plurality of hash units coupled to the storage elements. Each hash unit performs a hash operation using the first value and the second value to generate a corresponding hash result value. The processor further includes selection logic to select a hash result value from the hash result values generated by the plurality of hash units responsive to a selection input generated from another hash operation performed using the first value and the second value. A method includes predicting whether a branch instruction is taken based on a prediction value stored at an entry of a branch prediction table indexed by an index value selected from a plurality of values concurrently generated from an address value of the branch instruction and a branch history value representing a history of branch directions at the processor.
    Type: Application
    Filed: April 1, 2013
    Publication date: October 2, 2014
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Ramkumar Jayaseelan
  • SELECTIVE CACHE FILLS IN RESPONSE TO WRITE MISSES
    Publication number: 20140297961
    Abstract: A cache memory receives a request to perform a write operation. The request specifies an address. A first determination is made that the cache memory does not include a cache line corresponding to the address. A second determination is made that the address is between a previous value of a stack pointer and a current value of the stack pointer. A third determination is made that a write history indicator is set to a specified value. The write operation is performed in the cache memory without waiting for a cache fill corresponding to the address to be performed, in response to the first, second, and third determinations.
    Type: Application
    Filed: April 1, 2013
    Publication date: October 2, 2014
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Mithuna Thottethodi, Yasuko Eckert, Srilatha Manne
  • Method and apparatus for providing local screen data to a sink device
    Patent number: 8847969
    Abstract: A method and apparatus is provided for providing local screen data of a source device, such as a personal computer, to a sink device, such as a television, game console, or home theatre system, at a rate determined by the sink device. In one example, the method and apparatus responds to requests from the sink device to provide local screen data by serving the local screen data to the sink device from a circular buffer. The local screen data is written to the circular buffer in FIFO order based on the requests from the sink device, and read from the circular buffer based on the requests.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: September 30, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Daryl G. Sartain, Daniel A. Ivanciw
  • DDR 2D Vref training
    Patent number: 8850155
    Abstract: A method is provided for performing memory operations in response to instructions to perform a double data rate (DDR) memory reference voltage training in the voltage domain by a processing device and determining a DDR memory reference voltage and a DDR memory delay time based upon the memory operation. Computer readable storage media are also provided. A circuit is provided that includes a communication interface portion coupled to a memory and to a processing device. The circuit also includes a circuit portion, coupled to the communication interface portion that has a hardware state machine or an algorithm. The state machine or algorithm provides instructions to the processing device to perform a double data rate (DDR) reference voltage training in the voltage domain.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: September 30, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kevin M. Brandl, Oswin E. Housty, Gerald Talbot
  • Memory request scheduling based on thread criticality
    Patent number: 8850131
    Abstract: A method includes scheduling a memory request requested by a thread executing on a processing system. The scheduling is based on at least one of a number of critical sections being executed on the processing system by the thread and a number of other threads executing on the processing system being blocked from execution on the processing system by execution of the thread. In at least one embodiment of the invention, the thread is associated with a first application of a plurality of applications executing on the processing system and the scheduling is further based on an indicator of application priority.
    Type: Grant
    Filed: August 24, 2010
    Date of Patent: September 30, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Jaewoong Chung
  • Synchronizer circuits with failure-condition detection and correction
    Patent number: 8847647
    Abstract: An input signal and a reset signal are provided to respective inputs of a resettable flip-flop. The resettable flip-flop generates an output signal. The output signal transitions from a first logic state to a second logic state in response to corresponding transitions of the input signal and transitions from the second logic state to the first logic state in response to assertion of the reset signal. A warning signal is asserted in response to transitions of the input signal from the second logic state to the first logic state. A logic gate forwards the output signal when the warning signal is de-asserted and provides a signal in the first logic state in response to assertion of the warning signal.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: September 30, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Mark Buckler
  • Fault tolerant scannable glitch latch
    Patent number: 8850278
    Abstract: A fault tolerant scannable glitch latch for use with scan chains that enable reset, debug and repairability of machines and parts is described. A scan shift enable signal controls a switch such that a stuck-at zero fault on a data input line is prevented from driving voltage to a state node or pulling the state node high during a scan chain operation. Propagation of the stuck-at zero fault is therefore eliminated. The scan shift enable signal also controls a switch that enables a parallel path to ground for the scan data and state node which would otherwise have been driven high due to the stuck-at zero fault.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: September 30, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kevin M. Gillespie, Joseph R. Siegel, Dwight K. Elvey, Harry R. Fair
  • Cache for storing multiple forms of information and a method for controlling a cache storing multiple forms of information
    Patent number: 8843726
    Abstract: A cache is provided, including a data array having a plurality of entries configured to store a plurality of different types of data, and a tag array having a plurality of entries and configured to store a tag of the data stored at a corresponding entry in the data array and further configured to store an identification of the type of data stored in the corresponding entry in the data array.
    Type: Grant
    Filed: February 21, 2011
    Date of Patent: September 23, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Douglas Hunt
  • Technique for forming a passivation layer without a terminal metal
    Patent number: 8841140
    Abstract: By determining at least one surface characteristic of a passivation layer stack used for forming a bump structure, the situation after the deposition and patterning of a terminal metal layer stack may be “simulated,” thereby providing the potential for using well-established bump manufacturing techniques while nevertheless significantly reducing process complexity by omitting the deposition and patterning of the terminal metal layer stack.
    Type: Grant
    Filed: May 18, 2007
    Date of Patent: September 23, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Tobias Letz, Matthias Lehr, Joerg Hohage, Frank Kuechenmeister
  • Methods and systems to facilitate operation in unpinned memory
    Patent number: 8842126
    Abstract: In an embodiment, a method of processing memory requests in a first processing device is provided. The method includes generating a memory request associated with a memory address located in an unpinned memory space managed by an operating system running on a second processing device; and responsive to a determination that the memory address is not resident in a physical memory, transmitting a message to the second processing device. In response to the message, the operating system controls the second processing device to bring the memory address into the physical memory.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: September 23, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Warren Fritz Kruger, Philip J. Rogers, Mark Hummel
  • Systems and methods for deferring software implementation decisions until load time
    Patent number: 8843920
    Abstract: A software development method defers certain implementation details until load time. A programmer first annotates, in source code, a selected set of software components using metadata (such as Java-style annotations) that define one or more criteria—e.g., criteria relating to the state of the target hardware platform, the capabilities of the platform, or arbitrary user input. The annotated source code files are then compiled to create one or more intermediate code files (e.g., Java bytecode files). During load time of the resulting intermediate code files, one or more of the selected set of software components are loaded from the intermediate code files based on the criteria.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: September 23, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Gary Frost, Shrinivas Joshi
  • Global Efficient Application Power Management
    Publication number: 20140281592
    Abstract: A method, system and computer-readable medium for allocating power among computing resources are provided. The method calculates an activity level of a first computer resource. When the activity level is less than a threshold value, the method increases the power allocation to a second computing resource. When the activity level exceeds the threshold value, the method decreases the power allocation to the second computing resource.
    Type: Application
    Filed: March 18, 2013
    Publication date: September 18, 2014
    Applicant: Advanced Micro Devices, Inc.
    Inventors: William L. BIRCHER, Donald W. Cherepacha, Adam N.C. Clark
  • Power management in multi-GPU systems
    Patent number: 8839012
    Abstract: A method of power management is provided. The method includes detecting an event, assign a first responsibility to a first graphics processing unit (GPU) and a second responsibility to second GPU, and changing a power state of the first and second GPUs based on the first and second responsibilities, respectively. The first responsibility is different from the second responsibility.
    Type: Grant
    Filed: September 8, 2009
    Date of Patent: September 16, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Oleksandr Khodorkovsky
  • Methods and apparatus for compressing partial products during a fused multiply-and-accumulate (FMAC) operation on operands having a packed-single-precision format
    Patent number: 8838664
    Abstract: The disclosed embodiments relate to methods and apparatus for accurately, efficiently and quickly executing a fused multiply-and-accumulate instruction with respect to floating-point operands that have packed-single-precision format. The disclosed embodiments can speed up computation of a high-part of a result during a fused multiply-and-accumulate operation so that cycle delay can be reduced and so that power consumption can be reduced.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: September 16, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David Oliver, Debjit Dassarma, Hanbing Liu, Scott Hilker
  • Programmable clock driver
    Patent number: 8836403
    Abstract: A clock driver circuit supplies a clock signal with a drive strength determined according to one or more control signals supplied to the clock driver that vary during run-time. The clock driver is operated with a first drive strength in a non-resonant mode of operation of an associated clock network and with a second drive strength in a resonant mode of operation of the associated clock network, the first drive strength being higher than the second drive strength.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: September 16, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Visvesh S. Sathe, Srikanth Arekapudi, Samuel D. Naffziger, Manivannan Bhoopathy
  • Circuit board socket with support structure
    Patent number: 8837162
    Abstract: Various circuit board sockets and methods of manufacturing and using the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a socket that is operable to receive a circuit board. The socket includes a surface for seating a first portion of a circuit board, a floor and a first support structure projecting away from the floor to support a second portion of the circuit board. The support structure includes a plurality of nested frames.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: September 16, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Stephen Heng, Mahesh S. Hardikar
  • Decision feedback equalization with selectable tap
    Patent number: 8837569
    Abstract: A system generates a set of candidate signals based on a received signal, whereby each candidate signal represents an adjustment of the signal for a different amount of potential noise. The system selects one of the candidate signals based on a selected subset of previous samples and the values of the selected subset of samples. The subset of previous samples is selected based on a predicted noise pattern.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: September 16, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventor: David Joseph Block
  • Metallization system of a semiconductor device comprising extra-tapered transition vias
    Patent number: 8835303
    Abstract: In a metallization system of a semiconductor device, a transition via may be provided with an increased degree of tapering by modifying a corresponding etch sequence. For example, the resist mask for forming the via opening may be eroded once or several times in order to increase the lateral size of the corresponding mask opening. Due to the pronounced degree of tapering, enhanced deposition conditions may be accomplished during the subsequent electrochemical deposition process for commonly filling the via opening and a wide trench connected thereto.
    Type: Grant
    Filed: December 9, 2009
    Date of Patent: September 16, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Frank Feustel, Thomas Werner, Kai Frohberg
  • System, method, and computer program product for a tessellation engine using a geometry shader
    Patent number: 8836700
    Abstract: A method, system, and computer program product are disclosed for providing tessellated primitive data to a geometry shader. The method comprises computing a set of tessellated vertices and a computed set of connectivity data based on an original set of vertices and an original set of connectivity data, generating computed vertex data based on the original set of vertices and the set of tessellated vertices, receiving the computed set of connectivity data, requesting a subset of the computed vertex data based on the computed set of connectivity data, and processing primitives defined by the subset of the computed vertex data. The system and computer program product are further disclosed for accomplishing a similar result as the aforementioned method.
    Type: Grant
    Filed: May 27, 2009
    Date of Patent: September 16, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Vineet Goel