Abstract: Methods and apparatuses are provided for increased efficiency in a processor via control word prediction. The apparatus comprises an operational unit capable of determining whether an instruction will change a first control word to a second control word for processing dependent instructions. Execution units process the dependent instructions using a predicted control word and compare the second control word to the predicted control word. A scheduling unit causes the execution units to reprocess the dependent instructions when the predicted control word does not match the second control word. The method comprises determining that an instruction will change a first control word to a second control word and processing the dependent instructions using a predicted control word. The second control word is compared to the predicted control word and the dependent instructions are reprocessed using the second control word when the predicted control word does not match the second control word.

Abstract: The present invention provides a method of forming a transistor. The method includes forming a first layer of a first semiconductor material above an insulation layer. The first semiconductor material is selected to provide high mobility to a first carrier type. The method also includes forming a second layer of a second semiconductor material above the first layer of semiconductor material. The second semiconductor material is selected to provide high mobility to a second carrier type opposite the first carrier type. The method further includes forming a first masking layer adjacent the second layer and etching the second layer through the first masking layer to form at least one feature in the second layer. Each feature in the second layer forms an inverted-T shape with a portion of the second layer.

Abstract: A method for forming a semiconductor device is provided including processing a wafer having a target material, forming a multilevel photoresist structure having a protection layer over the target material, and forming a multilevel recess in the target material with the multilevel photoresist structure.

Abstract: Disclosed are methods, apparatus, and computer-readable media for generating output computer code that adds a 64-bit integer to a smaller-length integer having a length of less than 64 bits. Input computer code includes a loop that includes adding a 64-bit integer and a smaller-length integer. Output code is generated that represents the input code in a format such as assembly language or machine code. The output code includes instructions to convert the smaller-length integer to a 64-bit integer, such that the conversion is not performed during each loop execution. The smaller-length integer is converted by subtracting an offset from the 64-bit integer, adding the offset to the smaller-length integer, and zero-extending the smaller-length integer. The offset is determined based on the length of the smaller-length integer. The output code preserves the integer semantics of the smaller-length integer as required by the input code.

Abstract: A method for forming an integrated circuit system is provided including forming a semi-conducting layer over a substrate, forming a spacer stack having a gap filler adjacent to the semi-conducting layer and a inter-layer dielectric over the gap filler, forming a transition layer having a recess over the semi-conducting layer and adjacent to the spacer stack, and forming a metal layer in the recess.

Abstract: We report methods relating to scan warmup of integrated circuit devices. One such method may comprise loading a scan test stimulus to and unloading a scan test response from a first set of logic elements of an integrated circuit device at a scan clock first frequency equal to a test clock frequency; adjusting the scan clock from the first frequency to a second frequency by a scan warmup unit, wherein the scan clock second frequency is equal to a system clock frequency; and capturing the scan test response by a shift logic at the scan clock second frequency. We also report processors containing components configured to implement the method, and fabrication of such processors. The methods and their implementation may reduce di/dt events otherwise commonly occurring when testing logic elements of integrated circuit devices.

Abstract: An integrated circuit device comprising first circuitry including first logic devices and a clock tree for distributing a clock signal to the first logic devices and second circuitry comprising second logic devices, a first clock gater and a second clock gater. The first and second clock gaters comprise a programmable delay circuit.

Abstract: A method and apparatus for sorting data into spatial bins or buckets using a graphics processing unit (GPU). The method takes unsorted point data as input and scatters the points, in sorted order, into a set of bins. This key operation enables construction of a spatial data structure that is useful for applications such as particle simulation or collision detection. The disclosed method achieves better performance scaling than previous methods by exploiting geometry shaders to progressively trim the size of a working set. The method also leverages predicated rendering functionality to allow early termination without CPU/GPU synchronization. Furthermore, unlike previous techniques, the method can guarantee sorted output without requiring sorted input. This allows the method to be used to implement a form of bucket sort using the GPU.

Abstract: A system and method of providing directory cache coherence are disclosed. The system and method may include tracking the coherence state of at least one cache block contained within a region using a global directory, providing at least one region level sharing information about the least one cache block in the global directory, and providing at least one block level sharing information about the at least one cache block in the global directory. The tracking of the provided at least one region level sharing information and the provided at least one block level sharing information may organize the coherence state of the at least one cache block and the region.

Abstract: A method is provided for data compression. The data compression method transforms a square of data into a tile of data. The tile of data is then divided into quads of data that are converted into a representative element, a first delta element, a second delta element, a third delta element, and a control word. A new tile of data is then formed with the representative elements, and the process is repeated until a single representative element remains. The single representative element is then embedded into an output stream with the control words and corresponding delta elements. Decompression of the data is symmetrical to the encoding once the bit stream has been parsed.

Abstract: A multi-link input/output (I/O) interface uses both feed-forward and feedback signaling to reduce the impact of noise on data capture at a memory controller. To transfer data from a source module to a destination module, a defined pattern is communicated from the memory module along a master channel concurrent with the memory module providing data via one or more slave channels. Based on the phase of the defined pattern as it is received, the multi-link I/O interface feeds forward to the slave channels control signaling whose phase reflects a predicted noise pattern for the system. Each slave channel performs CDR by adjusting timing of its corresponding capture clock signal based on the fed forward control signaling and based on feedback signaling for the corresponding slave channel, whereby the feedback signaling reflects an error measurement between a phase of a capture clock signal and transitions in received data.

Abstract: A system and method for optimizing a flow of data traffic are provided. A plurality of tori are connected in a parallel tori interconnect. Each torus includes a plurality of nodes. The nodes in the torus are interconnected using links. A host in the network is connected to a subset of nodes where nodes in the subset are associated with different tori. The host transmits the packets to the parallel tori interconnect by selecting a node the subset of nodes. The packets are transmitted using links between from the node to the plurality of nodes in the torus, but not between the plurality of tori.

Abstract: A technique for configuring a computing system that allows for multiple computing systems and device populations to be supported by a single BIOS implementation is presented. In one embodiment, the technique includes processing topology map parameters that describe physical connections of a computing system, wherein the computing system includes a plurality of processing nodes; determining routing paths for traffic between the plurality of processing nodes; and determining a population of the plurality of processing nodes. In one embodiment, the determining the routing paths is performed during BIOS build time. In another embodiment, the determining the routing paths is performed during BIOS run time.

Abstract: Disclosed herein is a graphics-processing unit (GPU) having an internal memory for general-purpose use and applications thereof. Such a GPU includes a first internal memory, an execution unit coupled to the first internal memory, and an interface configured to couple the first internal memory to a second internal memory of an other processing unit. The first internal memory may comprise a stacked dynamic random access memory (DRAM) or an embedded DRAM. The interface may be further configured to couple the first internal memory to a display device. The GPU may also include another interface configured to couple the first internal memory to a central processing unit. In addition, the GPU may be embodied in software and/or included in a computing system.

Abstract: A memory cell system including providing a substrate, forming a charge-storing stack having silicon-rich nitride on the substrate, and forming a gate on the charge-storing stack.

Abstract: Embodiments described herein provide a method of arbitrating a processing resource. The method includes receiving a command to preempt a task and preventing additional wavefronts associated with the task from being processed. The method also includes evicting currently executing wavefronts associated with the task from being processed based upon predetermined criteria.

Abstract: Described is an aggregation device comprising a plurality of virtual network interface cards (vNICs) and an input/output (I/O) processing complex. The vNICs are in communication with a plurality of processing devices. Each processing device has at least one virtual machine (VM). The I/O processing complex is between the vNICs and at least one physical NIC. The I/O processing complex includes at least one proxy NIC and a virtual switch. The virtual switch exchanges data with a processing device of the plurality of processing devices via a communication path established by a vNIC of the plurality of vNICs between the at least one VM and at least one proxy NIC.

Abstract: Techniques for performing DC to DC power conversion in switch-mode converter circuits include combinations of dynamic switch shedding, phase shedding, symmetric phase circuit topologies, and asymmetric phase circuit topologies. In at least one embodiment of the invention, a method of operating a power converter circuit includes operating a first phase switch circuit portion using a first number of switch devices when the power converter circuit is configured in a first mode of operation. The first number is greater than zero. The method includes operating the first phase switch circuit portion using the first number of switch devices when the power converter circuit is configured in a second mode of operation. The method includes operating a second phase switch circuit portion using a second number of switch devices when the power converter circuit is configured in the second mode of operation. The second number is greater than the first number.

Abstract: A system and method using new PCI Express transaction layer packet headers so that unchanged header information within a burst of transactions does not need to be re-transmitted. After the first full packet header of a burst is sent, subsequent packet headers in the burst are smaller. Thus, more reduced headers can be transmitted over time with a resulting increased efficiency. Both sides of the PCI Express transaction must support this system and method for this approach to be enabled. Once enabled, both the PCI Express transmitter and receiver can use the regular full header PCI Express packets as well as the reduced header packets.

Abstract: By incorporating germanium material into thermal sensing diode structures, the sensitivity thereof may be significantly increased. In some illustrative embodiments, the process for incorporating the germanium material may be performed with high compatibility with a process flow for incorporating a silicon/germanium material into P-channel transistors of sophisticated semiconductor devices. Hence, temperature control efficiency may be increased with reduced die area consumption.