Abstract: A method of assembling a semiconductor chip device is provided that includes providing a circuit board including a surface with an aperture. A portion of a first heat spreader is positioned in the aperture. A stack is positioned on the first heat spreader. The stack includes a first semiconductor chip positioned on the first heat spreader and a substrate that has a first side coupled to the first semiconductor chip.

Abstract: A cluster tool may be operated on the basis of an enhanced sequencing regime in which the supply of substrates is controlled such that a planned time of maintenance is reached for two or more process chambers simultaneously. Consequently, the occurrence of non-correlated sequential down times of various process chambers may be significantly reduced, thereby enhancing throughput and availability of complex cluster tools.

Abstract: Methods and apparatus are provided, as an aspect of a combined CPU/APD architecture system, for discovering and reporting properties of devices and system topology that are relevant to efficiently scheduling and distributing computational tasks to the various computational resources of a combined CPU/APD architecture system. The combined CPU/APD architecture unifies CPUs and APDs in a flexible computing environment. In some embodiments, the combined CPU/APD architecture capabilities are implemented in a single integrated circuit, elements of which can include one or more CPU cores and one or more APD cores. The combined CPU/APD architecture creates a foundation upon which existing and new programming frameworks, languages, and tools can be constructed.

Abstract: A method and apparatus for branch determination is disclosed. The method includes a first command issuing within a computer processor. Execution of the first command by the computer processor includes evaluating one or more conditions to set one or more flags. Subsequent to the first command issuing, a second command is issued and executed. Execution of the second command includes causing the computer processor to wait until the one or more flags are set. Subsequent to the first and second commands issuing, a third command is issued and executed. Execution of the third command includes performing a jump operation based on a value of at least one of the one or more flags set by the first command.

Abstract: Circuit and methods provide for adjustable power consumption using a plurality of memory controllers. In one example, a first memory controller has a first power consumption level. A second memory controller has a second power consumption level that differs from the first power consumption level. Memory controller bypass logic is connected to the first and second memory controllers and selects for a memory client at least one of the first and second memory controllers in response to a change in a power conservation condition.

Abstract: A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal.

Abstract: The present invention provides a method and apparatus for bypassing silicon bugs. One exemplary embodiment of the method includes using a logic element formed on a substrate to detect a predefined trigger condition indicating onset of a functional bug during operation of a semiconductor device formed on the substrate. The method also includes modifying operation of the semiconductor device to avoid onset of the functional bug by taking a predefined action associated with the predefined trigger condition.

Abstract: An apparatus for executing an atomic memory transaction comprises a processing core in a multi-processing core system, where the processing core is configured to store an atomic program in a cache line. The apparatus further comprises an atomic program execution unit that is configured to execute the atomic program as a single atomic memory transaction with a guarantee of forward progress.

Abstract: A method includes updating a first tag access indicator of a storage structure. The tag access indicator indicates a number of accesses by a first thread executing on a processor to a memory resource for a portion of memory associated with a memory tag. The updating is in response to an access to the memory resource for a memory request associated with the first thread to the portion of memory associated with the memory tag. The method may include updating a first sum indicator of the storage structure indicating a sum of numbers of accesses to the memory resource being associated with a first access indicator of the storage structure for the first thread, the updating being in response to the access to the memory resource.

Abstract: Methods and apparatuses are provided for servicing an interrupt in a computer system. The method includes a device driver receiving an interrupt request. The device driver is responsive to the interrupt request to store interrupt data in a portion of the memory. The interrupt data includes identification of at least one processor of the plurality of processors capable of servicing the interrupt request; priority of the interrupt request; a thread context; and an address for instructions to service the interrupt request. The device driver then instructs the peripheral device to issue a memory write to the plurality of processors so that each may determine if it can use the thread context and the instructions to service the interrupt. A computer system is provided with the hardware needed to perform the method.

Abstract: An apparatus and method for per-node thermal control of processing nodes is disclosed. The apparatus includes a plurality of processing nodes, and further includes a power management unit configured to set a first frequency limit for at least one of the plurality of processing nodes responsive to receiving an indication of a first detected temperature greater than a first temperature threshold, wherein the first detected temperature is associated with the one of the plurality of processing nodes. The power management unit is further configured to set a second frequency limit for each of the plurality of processing nodes responsive to receiving an indication of a second temperature greater than a second temperature threshold.

Abstract: A branch predictor for use in a processor includes a Level 1 branch predictor, a Level 2 branch predictor, a match determining circuit, and an override determining circuit. The Level 1 branch predictor generates a Level 1 branch prediction. The Level 2 branch predictor generates a Level 2 branch prediction. The match determining circuit determines whether the Level 1 and Level 2 branch predictions match. The override determining circuit determines whether to override the Level 1 branch prediction with the Level 2 branch prediction. The Level 1 branch prediction is used when the Level 1 and Level 2 branch predictions match or when the Level 1 and Level 2 branch predictions do not match and the Level 1 branch prediction is not overridden. The Level 2 branch prediction is used when the Level 1 and Level 2 branch predictions do not match and the Level 1 branch prediction is overridden.

Abstract: A crossbar switch with primary and secondary pickers is described herein. The crossbar switch includes a crossbar switch command scheduler that schedules commands that are to be routed across the crossbar from multiple source ports to multiple destination ports. The crossbar switch command scheduler uses primary and secondary pickers to schedule two commands per clock cycle. The crossbar switch may also include a dedicated response bus, a general purpose bus and a dedicated command bus. A system request interface may include dedicated command and data packet buffers to work with the primary and secondary pickers.

Abstract: A processing core in a multi-processing core system is configured to execute a sequence of instructions as a single atomic memory transaction. The processing core validates that the sequence meets a set of one or more atomicity criteria, including that no instruction in the sequence instructs the processing core to access shared memory. After validating the sequence, the processing core executes the sequence as a single atomic memory transaction, such as by locking a source cache line that stores shared memory data, executing the validated sequence of instructions, storing a result of the sequence into the source cache line, and unlocking the source cache line.

Abstract: A method and an apparatus for power filtering in a Translation Look-aside Buffer (TLB) are described. In the method and apparatus, power consumption reduction is achieved by suppressing physical address (PA) reads from random access memory (RAM) if the previously translated linear address (LA), or virtual address (VA), is the same as the currently requested LA. To provide the correct translation, the output of the TLB is maintained if the previously translated LA and the LA currently requested for translation are the same.

Abstract: A method for comparing content addressable memory (CAM) elements is disclosed. Binary values are stored in a pair of CAM elements. A comparison value is provided to a group of comparators, the comparison value based on the binary value stored in the pair of CAM elements. A match value is provided to the group of comparators, the match value corresponding to a binary value pair to be compared with the binary value stored in the pair of CAM elements. A positive match result value is output from a selected group of comparators via an output line in response to the comparison value matching the match value.

Abstract: A semiconductor device fabrication process includes forming insulating mandrels over replacement metal gates on a semiconductor substrate with first gates having sources and drains and at least one second gate being isolated from the first gates. Mandrel spacers are formed around each insulating mandrel. The mandrels and mandrel spacers include the first insulating material. A second insulating layer of the second insulating material is formed over the transistor. One or more first trenches are formed to the sources and drains of the first gates by removing the second insulating material between the insulating mandrels. A second trench is formed to the second gate by removing portions of the first and second insulating materials above the second gate. The first trenches and the second trench are filled with conductive material to form first contacts to the sources and drains of the first gates and a second contact to the second gate.

Abstract: A system and method are disclosed for improving the performance of compiled Java code. A native code management module determines the available processor resources associated with a target information processing system, their respective instruction set architecture (ISA), and possible native code compilation optimization processes. The native code management module then generates compiler parameter permutations, which are iteratively provided to a just-in-time (JIT) compiler. Each compiler parameter permutation is used by JIT compiler to generate a native code compilation iteration. Each of the resulting native code compilation iterations are executed by the JVM and their respective performance is measured to determine the best performing native code compilation iteration.

Abstract: A system and method for efficient improvement of branch prediction in a microprocessor with negligible impact on die-area, power consumption, and clock cycle period. It is determined if a program counter (PC) register contains a polymorphic indirect unconditional branch (PIUB) instruction. One determination may be searching a table with a portion or all of a PC of past PIUB instructions. If a hit occurs in this table, the global shift register (GSR) is updated by shifting a portion of the branch target address into the GSR, rather than updating the GSR with a taken/not-taken prediction bit. The stored value in the GSR is input into a hashing function along with the PC in order to index prediction tables such as a pattern history table (PHT), a branch target buffer (BTB), an indirect target array, or other. The updated value due to the PIUB instruction improves the accuracy of the prediction tables.

Abstract: A system and method of data communications between a first device and a second device is disclosed. The method includes generating a first clock signal at the first device and generating a second clock signal having a phase offset from the first clock signal. The clock signals are transmitted from the first device to the second device. The method further includes regulating transmission of a read strobe signal sent from the second device to the first device utilizing the first clock signal. The method also includes regulating transmission of a data transfer signal sent from the second device to the first device utilizing the second clock signal.