Patents Assigned to Advanced Semiconductor Engineering, Inc.
  • Publication number: 20220148974
    Abstract: An assembly structure includes a core-computing section and a sub-computing section. The core-computing section has a first surface and a second surface opposite to the first surface. The core-computing section includes at least one conductive via electrically connecting the first surface and the second surface. The sub-computing section has a first surface stacked on the first surface of the core-computing section and a second surface opposite to the first surface. The sub-computing section includes at least one conductive via electrically connecting the first surface and the second surface. The assembly structure includes a first signal transmission path and a second signal transmission path. The first signal transmission path is between the at least one conductive via of the sub-computing section and the at least one conductive via of the core-computing section.
    Type: Application
    Filed: January 25, 2022
    Publication date: May 12, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Yuan KUNG, Hung-Yi LIN
  • Publication number: 20220148936
    Abstract: A package structure and a circuit layer structure are provided in the present disclosure. The package structure includes a wiring structure, a first electronic device, a second electronic device and at least one dummy trace. The wiring structure includes a plurality of interconnection traces. The first electronic device and the second electronic device are disposed on the wiring structure, and electrically connected to each other through the interconnection traces. The dummy trace is adjacent to the interconnection traces. A mechanical strength of the at least one dummy trace is less than a mechanical strength of one of the interconnection traces.
    Type: Application
    Filed: November 6, 2020
    Publication date: May 12, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen-Long LU
  • Publication number: 20220148954
    Abstract: A wiring structure and a method for manufacturing the same are provided. The wiring structure includes a conductive structure, an intermediate structure and a seed layer. The conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The conductive structure defines an accommodating hole. The intermediate structure is bonded to an inner surface of the accommodating hole. The seed layer is bonded to the accommodating hole through the intermediate structure.
    Type: Application
    Filed: November 6, 2020
    Publication date: May 12, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen Hung HUANG
  • Publication number: 20220148989
    Abstract: A semiconductor package includes a first substrate, a first flow channel and a second flow channel. The first flow channel is on the first substrate. The second flow channel is on the first substrate and in fluid communication with the first flow channel. The second flow channel is spaced from an inlet and an outlet of the first flow channel. The first flow channel and the second flow channel constitute a bonding region of the first substrate.
    Type: Application
    Filed: November 6, 2020
    Publication date: May 12, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yung-Sheng LIN, Yun-Ching HUNG, An-Hsuan HSU, Chung-Hung LAI
  • Patent number: 11328989
    Abstract: A wiring structure and a method for manufacturing the same are provided. The wiring structure includes an upper conductive structure, a lower conductive structure and a redistribution structure. The upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The redistribution structure is disposed between the upper conductive structure and the lower conductive structure to electrically connect the upper conductive structure and the lower conductive structure. The redistribution structure includes a dielectric structure and a redistribution layer embedded in the dielectric structure. The redistribution layer includes at least one circuit layer.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: May 10, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Patent number: 11329007
    Abstract: A wiring structure includes a conductive structure, a surface structure and at least one through via. The conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The surface structure is disposed adjacent to a top surface of the conductive structure. The through via extends through the surface structure and extending into at least a portion of the conductive structure.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: May 10, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Yan Wen Chung, Huei-Shyong Cho
  • Patent number: 11329017
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first electronic component having an active surface and a backside surface opposite to the active surface and a first antenna layer disposed on the backside surface of the first electronic component. The semiconductor device package further includes a first dielectric layer covering the first antenna layer and a second antenna layer disposed over the first antenna layer. The second antenna layer is spaced apart from the first antenna layer by the first dielectric layer. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: May 10, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wei-Tung Chang, Cheng-Nan Lin
  • Patent number: 11328999
    Abstract: A semiconductor device package includes a lower-density substrate and a higher-density substrate. The higher-density substrate is attached to the lower-density substrate. The higher-density substrate has a first interconnection layer and a second interconnection layer disposed over the first interconnection layer. A thickness of the first interconnection layer is different from a thickness of the second interconnection layer.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: May 10, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Fu-Chen Chu, Hung-Chun Kuo, Chen-Chao Wang
  • Patent number: 11329016
    Abstract: A semiconductor device package includes a carrier, an emitting device, a first building-up circuit and a first package body. The carrier has a first surface, a second surface opposite to the first surface and a lateral surface extending from the first surface to the second surface. The emitting element is disposed on the first surface of carrier. The first building-up circuit is disposed on the second surface of the carrier. The first package body encapsulates the lateral surface of the carrier.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: May 10, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Meng-Wei Hsieh, Chieh-Chen Fu
  • Patent number: 11329015
    Abstract: A semiconductor device package includes an emitting device and a first building-up circuit. The emitting device defines a cavity in the emitting device. The first building-up circuit is disposed on the emitting device.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: May 10, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Meng-Wei Hsieh
  • Publication number: 20220139872
    Abstract: A method and a system for manufacturing a semiconductor package structure are provided. The method includes: (a) providing a package body including at least one semiconductor device encapsulated in an encapsulant; (b) providing a flattening force to the package body; (c) thinning the package body after (b); (d) attaching a film to the package body; and (e) releasing the flattening force after (d).
    Type: Application
    Filed: October 30, 2020
    Publication date: May 5, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Che-Ting LIU, Jheng-Yu HONG, Yu-Ting LU, Po-Chun LEE, Chih-Hsiang HSU
  • Publication number: 20220141971
    Abstract: A semiconductor device package includes a display device, an encapsulation layer disposed in direct contact with the display device, and a reinforced structure surrounded by the encapsulation layer. The reinforced structure is spaced apart from a surface of the display device. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Application
    Filed: January 11, 2022
    Publication date: May 5, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ming-Hung CHEN, Yung I. YEH, Chang-Lin YEH, Sheng-Yu CHEN
  • Publication number: 20220139854
    Abstract: A bonding structure, a package structure, and a method for manufacturing a package structure are provided. The package structure includes a first substrate, a first passivation layer, a first conductive layer, and a first conductive bonding structure. The first passivation layer is disposed on the first substrate and has an upper surface. The first passivation layer and the first substrate define a first cavity. The first conductive layer is disposed in the first cavity and has an upper surface. A portion of the upper surface of the first conductive layer is below the upper surface of the first passivation layer. The first conductive bonding structure is disposed on the first conductive layer.
    Type: Application
    Filed: October 29, 2020
    Publication date: May 5, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wan Yu CHANG, Shao Hsuan CHUANG
  • Publication number: 20220140467
    Abstract: A semiconductor device package includes a substrate, an air cavity, a radiator, and a director. The substrate has a top surface. The air cavity is disposed within the substrate. The air cavity has a first sidewall and a second sidewall opposite to the first sidewall. The radiator is disposed adjacent to the first sidewall of the air cavity. The director is disposed adjacent to the second sidewall of the air cavity.
    Type: Application
    Filed: October 29, 2020
    Publication date: May 5, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ting Ruei CHEN, Hung-Hsiang CHENG, Guo-Cheng LIAO, Yun-Hsiang TIEN
  • Publication number: 20220139726
    Abstract: A method and a system for manufacturing a semiconductor package structure are provided. The method includes: (a) measuring an amount of a molding powder; (b) controlling the amount of a molding powder; and (c) dispensing the molding powder on an assembly structure including a carrier and at least one semiconductor device disposed on the carrier.
    Type: Application
    Filed: October 30, 2020
    Publication date: May 5, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Chenghan SHE
  • Publication number: 20220139824
    Abstract: At least some embodiments of the present disclosure relate to a wiring structure and a method for manufacturing a wiring structure. The wiring structure includes a conductive structure, a first fan-out structure, and a second fan-out structure. The first fan-out structure is disposed on the conductive structure and includes a first circuit layer. The second fan-out structure is disposed on the conductive structure, and includes a second circuit layer. A thickness of the first circuit layer is different from a thickness of the second circuit layer.
    Type: Application
    Filed: November 5, 2020
    Publication date: May 5, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chih-Yi HUANG, Chen-Chao WANG, Mi-Chun HUNG
  • Publication number: 20220139812
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a carrier, a first encapsulant, and an interposer. The first encapsulant is on the carrier and defines a cavity. The interposer is disposed between the first encapsulant and the cavity. The first encapsulant covers a portion of the interposer.
    Type: Application
    Filed: November 3, 2020
    Publication date: May 5, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Che HUANG, Chang Chin TSAI
  • Publication number: 20220139751
    Abstract: A method for manufacturing a semiconductor package structure and a clamp apparatus are provided. The method includes: (a) providing a package body disposed on a chuck, wherein the package body includes at least one semiconductor element encapsulated in an encapsulant; (b) moving a pressing tool transversely to above the package body; and (c) pressing the package body on the chuck through the pressing tool.
    Type: Application
    Filed: October 30, 2020
    Publication date: May 5, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Yun Di HONG
  • Publication number: 20220139866
    Abstract: A method for manufacturing a semiconductor package structure and a semiconductor manufacturing apparatus are provided. The method includes: (a) providing a package body disposed on a chuck, wherein the package body includes at least one semiconductor element encapsulated in an encapsulant; and (b) sucking the package body through the chuck to create a plurality of negative pressures on a bottom surface of the package body sequentially from an inner portion to an outer portion of the package body.
    Type: Application
    Filed: October 30, 2020
    Publication date: May 5, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Yun Di HONG
  • Patent number: 11322428
    Abstract: A semiconductor device package includes a substrate, a first semiconductor die, a conductive via, a first contact pad and a second contact pad. The substrate includes a first surface, and a second surface opposite to the first surface, the substrate defines a cavity through the substrate. The first semiconductor die is disposed in the cavity, wherein the first semiconductor die includes an active surface adjacent to the first surface, and an inactive surface. The conductive via penetrates through the substrate. The first contact pad is exposed from the active surface of the first semiconductor die and adjacent to the first surface of the substrate. The second contact pad is disposed on the first surface of the substrate, wherein the second contact pad is connected to a first end of the conductive via.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: May 3, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: You-Lung Yen, Bernd Karl Appelt