Patents Assigned to Advanced Semiconductor Engineering, Inc.
  • Publication number: 20240170364
    Abstract: A semiconductor device package and a method of manufacturing a semiconductor device package are provided. The semiconductor device package includes at least one electronic component, a heat source, and a heat dissipation element. The heat source is adjacent to the electronic component. The heat dissipation element is disposed adjacent to the heat source and the electronic component. The heat dissipation element includes a heat transmitting structure configured to reduce heat, which is from the heat source, through the heat dissipation element, and transmitting in a direction toward the electronic component.
    Type: Application
    Filed: November 23, 2022
    Publication date: May 23, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hung-Hsien HUANG, Wen Chun WU, Chih-Pin HUNG
  • Publication number: 20240170829
    Abstract: The present disclosure provides an electronic package. The electronic package includes an antenna structure having a first antenna and a second antenna at least partially covered by the first antenna. The electronic package also includes a directing element covering the antenna structure. The directing element has a first portion configured to direct a first electromagnetic wave having a first frequency to transmit via the first antenna and a second portion configured to direct a second electromagnetic wave having a second frequency different from the first frequency to transmit via the second antenna. A method of manufacturing an electronic package is also provided.
    Type: Application
    Filed: January 30, 2024
    Publication date: May 23, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jenchun CHEN, Ya-Wen LIAO
  • Publication number: 20240170345
    Abstract: A method of manufacturing a circuit pattern structure, a measurement method, and a circuit pattern structure are provided. The method of manufacturing the circuit pattern structure includes: forming a dielectric layer; forming at least one first pad at least partially in the dielectric layer; forming a second pad adjacent to the at least one first pad and having a height greater than that of the at least one first pad.
    Type: Application
    Filed: November 17, 2022
    Publication date: May 23, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Kai LIN, Chih-Cheng LEE
  • Publication number: 20240170396
    Abstract: A package structure is provided. The package structure includes an encapsulant and an interposer. The encapsulant has a top surface and a bottom surface opposite to the top surface. The interposer is encapsulated by the encapsulant. The interposer includes a main body, an interconnector, and a stop layer. The main body has a first surface and a second surface opposite to the first surface. The interconnector is disposed on the first surface and exposed from the top surface of the encapsulant. The stop layer is on the second surface, wherein a bottom surface of the stop layer is lower than the second surface.
    Type: Application
    Filed: January 30, 2024
    Publication date: May 23, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yung-Shun CHANG, Sheng-Wen YANG, Teck-Chong LEE, Yen-Liang HUANG
  • Publication number: 20240170603
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a substrate having a first surface and a second surface opposite to the first surface, an optical device disposed on the first surface of the substrate, and an electronic device disposed on the second surface of the substrate. A power of the electronic device is greater than a power of the optical device. A vertical projection of the optical device on the first surface is spaced apart from a vertical projection of the electronic device on the second surface by a distance greater than zero.
    Type: Application
    Filed: January 30, 2024
    Publication date: May 23, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Mei-Yi WU, Chang Chin TSAI, Bo-Yu HUANG, Ying-Chung CHEN
  • Publication number: 20240170437
    Abstract: A package structure is disclosed. The package structure includes a first substrate, a second substrate, a gap, and a directing structure. The second substrate is disposed under the first substrate. The gap is between the first substrate and the second substrate. The gap includes a first region and a second region. The first region is configured to accommodate a filling material. The directing structure is disposed in a flow path of the filling material and configured to reduce a migration of the filling material from the first region to the second region.
    Type: Application
    Filed: November 23, 2022
    Publication date: May 23, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chun Fu KUO, Shang Min CHUANG, Ching Hung CHUANG, Hsu Feng TSENG, Jia Zhen WANG
  • Publication number: 20240168238
    Abstract: A recessed portion in a semiconductor substrate and a method of forming the same are provided. The method comprises: forming a mask on the semiconductor substrate; forming a protection layer on a top surface of the mask and on at least one sidewall of the mask, and on at least one surface of the semiconductor substrate exposed by the mask; performing a first etching process to remove the protection layer on the top surface of the mask and on a bottom surface of the semiconductor substrate exposed by the mask; and performing a second etching process to remove the remaining protection layer and to etch the semiconductor substrate to form the recessed portion. In this way, a recessed portion with relatively smooth and vertical sidewalls can be realized.
    Type: Application
    Filed: January 30, 2024
    Publication date: May 23, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shao Hsuan CHUANG, Huang-Hsien CHANG
  • Publication number: 20240170302
    Abstract: A method and a system for manufacturing a semiconductor package structure are provided. The method includes: (a) measuring an amount of a molding powder; (b) controlling the amount of a molding powder; and (c) dispensing the molding powder on an assembly structure including a carrier and at least one semiconductor device disposed on the carrier.
    Type: Application
    Filed: January 30, 2024
    Publication date: May 23, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Chenghan SHE
  • Patent number: 11988553
    Abstract: An optical module is disclosed. The optical module includes a carrier, an optical emitter disposed over the carrier, and a monitor disposed over the carrier and configured to adjust a property of a first light emitted from the optical emitter.
    Type: Grant
    Filed: September 20, 2022
    Date of Patent: May 21, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Kuo Sin Huang, Tien-Chia Liu, Ko-Fan Tsai, Cheng-Te Chou, Yan-Te Chou
  • Patent number: 11990385
    Abstract: An electronic device is provided. The electronic device includes an electronic component and a heat dissipation structure. The electronic component has a passive surface and a plurality of conductive vias exposed from the passive surface. The heat dissipation structure is disposed on the passive surface and configured to transmit a plurality of independent powers to the conductive vias through the passive surface.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: May 21, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Li-Chieh Hung, Hung-Chun Kuo
  • Patent number: 11991827
    Abstract: An electronic device is disclosed. The electronic device includes a system board and a first set of electronic devices disposed over the system board. Each of the first set of electronic devices comprises a processing unit and a carrier carrying the processing unit. The electronic device also includes a first interconnection structure electrically connected with the processing unit through the carrier and configured to receive a first power from a first power supply unit and to transmit the first power to the processing unit.
    Type: Grant
    Filed: October 14, 2022
    Date of Patent: May 21, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chun-Yen Ting, Pao-Nan Lee, Hung-Chun Kuo, Jung Jui Kang, Chang Chi Lee
  • Publication number: 20240162612
    Abstract: The present disclosure provides an electronic device. The electronic device includes a first transceiving element, a second transceiving element disposed over the first transceiving element, and a radiating structure configured to radiate a first EM wave having a lower frequency and a second EM wave having a higher frequency. The first transceiving element and the second transceiving element are collectively configured to provide a higher gain or bandwidth for the first EM wave than for the second EM wave.
    Type: Application
    Filed: November 10, 2022
    Publication date: May 16, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Po-An LIN, Guan-Wei CHEN, Shih-Wen LU
  • Publication number: 20240164021
    Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.
    Type: Application
    Filed: January 23, 2024
    Publication date: May 16, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Fan CHEN, Chien-Hao WANG
  • Patent number: 11985479
    Abstract: An electronic module is provided. The electronic module includes a first transducer and a second transducer. The first transducer is configured to radiate a first ultrasonic wave. The second transducer is configured to radiate a second ultrasonic wave. The first transducer and the second transducer are disposed on noncoplanar surfaces.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: May 14, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chih Lung Lin, Kuei-Hao Tseng, Kai Hung Wang
  • Patent number: 11982853
    Abstract: An optoelectronic package and a method of manufacturing an optoelectronic package are provided. The optoelectronic package includes a carrier. The carrier includes a first region and a second region. The first region is configured to supply power to a processing unit disposed on the carrier. The second region is for accommodating at least one optoelectronic device electrically coupled to the processing unit.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: May 14, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jr-Wei Lin, Mei-Ju Lu
  • Publication number: 20240154642
    Abstract: The present disclosure provides an electronic module including a circuit including a transmitting part and a receiving part physically separated from the transmitting part. The electronic module also includes an element isolated from the circuit and configured to block electrical interference between the transmitting part and the receiving part.
    Type: Application
    Filed: January 16, 2024
    Publication date: May 9, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shih-Wen LU, Chun-Jen CHEN, Po-Hsiang TSENG, Hsin-Han LIN, Ming-Lun YU
  • Publication number: 20240153920
    Abstract: An electronic device is disclosed. The electronic device includes a first conductive plate and a first electronic component. The first conductive plate includes a first connecting portion. The first electronic component supports the first conductive plate through the first connecting portion. The first connecting portion is electrically connected to the first electronic component and configured to buffer stress from the first conductive plate to the first electronic component.
    Type: Application
    Filed: November 9, 2022
    Publication date: May 9, 2024
    Applicants: Advanced Semiconductor Engineering, Inc., UNIVERSAL SCIENTIFIC INDUSTRIAL (SHANGHAI) CO., LTD.
    Inventors: Yi-Hung HOU, Yung-Fa CHEN, Sheng-Chia CHEN
  • Publication number: 20240155758
    Abstract: An electronic device is provided. The electronic device includes a first dielectric layer, an electronic element, an encapsulant, and a second dielectric layer. The first dielectric layer has a first coefficient of thermal expansion (CTE). The electronic element is disposed over the first dielectric layer. The encapsulant encapsulates the electronic element and has a second CTE. The second dielectric layer is disposed over the encapsulant and having a third CTE. The second CTE ranges between the first CTE and the third CTE.
    Type: Application
    Filed: November 4, 2022
    Publication date: May 9, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien Lin CHANG CHIEN, Yuan-Chun TAI, Yu Hsin CHANG CHIEN, Chiu-Wen LEE, Chang Chi LEE
  • Patent number: 11978706
    Abstract: An electronic package structure, an electronic substrate, and a method of manufacturing an electronic package structure are provided. The electronic package structure includes a substrate. The substrate includes a bonding region and an alignment structure. The bonding region is located at a side of the substrate and configured to bond with an electronic component. The alignment structure is located at the side of the substrate and out of the bonding region and configured to providing a fiducial mark for position-aligning, wherein the alignment structure comprises a first region and a second region visually distinct from the first region.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: May 7, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shun-Tsat Tu, Pei-Jen Lo
  • Publication number: 20240145319
    Abstract: A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.
    Type: Application
    Filed: January 2, 2024
    Publication date: May 2, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tsung-Yu LIN, Pei-Yu WANG, Chung-Wei HSU