Patents Assigned to Advanced Semiconductor Engineering, Inc.
  • Patent number: 10937761
    Abstract: A semiconductor device includes: a substrate having a first surface and a second surface opposite to the first surface; an electronic component disposed on the first surface of the substrate; a sensor disposed adjacent to the second surface of the substrate; an electrical contact disposed on the first surface of the substrate; and a package body exposing a portion of the electrical contact.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: March 2, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chih-Ming Hung, Meng-Jen Wang, Tsung-Yueh Tsai, Jen-Kai Ou
  • Patent number: 10939561
    Abstract: A wiring structure includes a first dielectric layer, a second dielectric layer adjacent to the first dielectric layer, and a conductive region. The first dielectric layer defines a first opening, and the second dielectric layer defines a second opening. The conductive region includes a conductive via filling the first opening and the second opening. The conductive region further includes a first conductive trace embedded in the second dielectric layer and electrically connected with the conductive via. The conductive region includes a sidewall traversing through a thickness of the second dielectric layer with a substantial linear profile. A method of manufacturing a wiring structure is also disclosed.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: March 2, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Min Lung Huang
  • Publication number: 20210057398
    Abstract: A semiconductor device package includes a first substrate, a dielectric layer, a thin film transistor (TFT) and an electronic component. The first substrate has a first surface and a second surface opposite to the first surface. The dielectric layer is disposed on the first surface of the first substrate. The dielectric layer has a first surface facing away from the first substrate and a second surface opposite to the first surface. The TFT layer is disposed on the dielectric layer. The electronic component is disposed on the second surface of the first substrate. A roughness of the first surface of the dielectric layer is less than a roughness of the first surface of the first substrate.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 25, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ming-Hung CHEN, Sheng-Yu CHEN, Chang-Lin YEH, Yung-I YEH
  • Publication number: 20210057572
    Abstract: A semiconductor device package includes a display device, an electronic module and a conductive adhesion layer. The display device includes a first substrate and a TFT layer. The first substrate has a first surface and a second surface opposite to the first surface. The TFT layer is disposed on the first surface of the first substrate. The electronic module includes a second substrate and an electronic component. The second substrate has a first surface facing the second surface of the first substrate and a second surface opposite to the first surface. The electronic component is disposed on the second surface of the second substrate. The conductive adhesion layer is disposed between the first substrate and the second substrate.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 25, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ming-Hung CHEN, Sheng-Yu CHEN, Chang-Lin YEH, Yung-I YEH
  • Publication number: 20210057356
    Abstract: A semiconductor package device includes a wiring structure, a semiconductor chip and an encapsulant. The semiconductor chip is electrically connected to the wiring structure. The encapsulant is disposed on the wiring structure and covers the semiconductor chip. A roughness (Ra) of a surface of the encapsulant is about 5 nm to about 50 nm.
    Type: Application
    Filed: August 21, 2019
    Publication date: February 25, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen-Long LU
  • Patent number: 10930802
    Abstract: A semiconductor device package includes a substrate, a first encapsulant and a second encapsulant. The substrate has an optical region and a surface-mount technology (SMT) device region. The first encapsulant includes a first portion disposed on the optical region and covers the optical region and a second portion disposed on the SMT device region and covers the SMT device region. The second encapsulant is disposed on the substrate and covers at least a portion of the second portion of the first encapsulant and a portion of the first portion of the first encapsulant.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: February 23, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Chanyuan Liu
  • Patent number: 10930627
    Abstract: A semiconductor device package includes a first semiconductor device having a first surface, an interconnection element having a surface substantially coplanar with the first surface of the first semiconductor device, a first encapsulant encapsulating the first semiconductor device and the interconnection element, and a second semiconductor device disposed on and across the first semiconductor device and the interconnection element.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: February 23, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chang-Yu Lin, Chi-Han Chen, Chieh-Chen Fu
  • Patent number: 10932032
    Abstract: An acoustic device includes a first chamber, a first through hole, a vibration structure, and a separation structure. The first chamber includes a first end and a second end. The first through hole is defined at the first end of the first chamber. The vibration structure is disposed at the second end of the first chamber and is configured to transmit an acoustic wave away from the first chamber. The separation structure is disposed within the first chamber and divides the first chamber into a first sub-chamber and a second sub-chamber. The separation structure defines a second through hole connecting the first sub-chamber and the second sub-chamber.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: February 23, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Ming-Tau Huang
  • Publication number: 20210050649
    Abstract: A semiconductor device package includes a substrate, a first antenna and a second antenna. The substrate has a first surface and a second surface opposite to the first surface. The first antenna pattern is disposed over the first surface of the substrate. The first antenna pattern has a first bandwidth. The first antenna pattern has a first port configured to generate a magnetic field. The second antenna pattern is disposed over the first surface of the substrate. The second antenna pattern has a second bandwidth different from the first bandwidth. A prolonged line of an edge of the first antenna pattern parallel to the magnetic field generated by the first port of the first antenna pattern is spaced apart from the second antenna pattern.
    Type: Application
    Filed: August 12, 2019
    Publication date: February 18, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shao-En HSU, Huei-Shyong CHO, Shih-Wen LU
  • Publication number: 20210050273
    Abstract: The present disclosure provides a semiconductor package structure having a semiconductor die having an active surface, a conductive bump on the active surface, configured to electrically couple the semiconductor die to an external circuit, the conductive bump having a bump height, a dielectric encapsulating the semiconductor die and the conductive bump, and a plurality of fillers in the dielectric, each of the fillers comprising a diameter, wherein a maximum diameter of the fillers is smaller than the bump height.
    Type: Application
    Filed: August 14, 2019
    Publication date: February 18, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ya-Yu HSIEH, Chin-Li KAO, Chung-Hsuan TSAI, Chia-Pin CHEN
  • Publication number: 20210043719
    Abstract: A semiconductor device package includes a substrate, a first patterned conductive layer, a second patterned conductive layer, a dielectric layer, a third patterned conductive layer and a connector. The substrate has a top surface. The first patterned conductive layer is on the top surface of the substrate. The second patterned conductive layer contacts the first patterned conductive layer. The second patterned conductive layer includes a first portion, a second portion and a third portion. The second portion is connected between the first portion and the third portion. The dielectric layer is on the top surface of the substrate. The dielectric layer covers the first patterned conductive layer and surrounds the second portion and the third portion of the second patterned conductive layer. The first portion of the second patterned conductive layer is disposed on the dielectric layer.
    Type: Application
    Filed: October 28, 2020
    Publication date: February 11, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Hua CHEN, Teck-Chong LEE
  • Publication number: 20210043527
    Abstract: A semiconductor device package includes a carrier, a first interposer disposed and a second interposer. The second interposer is stacked on the first interposer, and the first interposer is mounted to the carrier. The combination of the first interposer and the second interposer is substantially T-shaped.
    Type: Application
    Filed: August 9, 2019
    Publication date: February 11, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hao-Chih HSIEH, Tun-Ching PI, Sung-Hung CHIANG, Yu-Chang CHEN
  • Publication number: 20210043604
    Abstract: A semiconductor package structure includes a substrate, a first semiconductor die, a first dielectric, a second semiconductor die, and a second dielectric. The substrate has a first surface. The first semiconductor die is disposed on the first surface. The first dielectric encapsulates the first semiconductor die. The second semiconductor die is disposed on the first surface and adjacent to the first semiconductor die. The second dielectric encapsulates the second semiconductor die. The first dielectric is in contact with the second dielectric. An average filler size in the first dielectric is substantially greater than an average filler size in the second dielectric.
    Type: Application
    Filed: August 6, 2019
    Publication date: February 11, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Hsu-Nan FANG
  • Patent number: 10916429
    Abstract: A semiconductor device package includes: a redistribution stack including a dielectric layer defining a first opening; and a redistribution layer (RDL) disposed over the dielectric layer and including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending from the first portion of the first trace, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, the first opening in the dielectric layer has a maximum width along the first transverse direction, and the maximum width of the second portion of the first trace is less than the maximum width of the first opening.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: February 9, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: John Richard Hunt, William T. Chen, Chih-Pin Hung, Chen-Chao Wang
  • Patent number: 10916492
    Abstract: A semiconductor substrate and a method of manufacturing the same are provided. The semiconductor substrate includes a carrier and a conductive post. The carrier has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The carrier has a through hole extending between the first surface and the second surface. The carrier has a first opening on the lateral surface. The conductive post is disposed within the through hole.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: February 9, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tsann Huei Lee, Lu-Ming Lai
  • Publication number: 20210033785
    Abstract: An optical communication package structure includes a wiring structure, at least one via structure, a redistribution structure, at least one optical device and at least one electrical device. The wiring structure includes a main portion and a conductive structure disposed on an upper surface of the main portion. The main portion defines at least one through hole extending through the main portion. The via structure is disposed in the at least one through hole of the main portion and electrically connected to the conductive structure. The redistribution structure is disposed on a lower surface of the main portion and electrically connected to the via structure. The optical device is disposed adjacent to the upper surface of the main portion and electrically connected to the conductive structure. The electrical device is disposed on and electrically connected to the conductive structure.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Hsuan WU, Yung-Hui WANG
  • Publication number: 20210035908
    Abstract: A semiconductor device package includes a first circuit layer, a second circuit layer, a first semiconductor die and a second semiconductor die. The first circuit layer includes a first surface and a second surface opposite to the first surface. The second circuit layer is disposed on the first surface of the first circuit layer. The first semiconductor die is disposed on the first circuit layer and the second circuit layer, and electrically connected to the first circuit layer and the second circuit layer. The second semiconductor die is disposed on the second circuit layer, and electrically connected to the second circuit layer.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chih-Cheng LEE, Kuang Hsiung CHEN
  • Publication number: 20210035912
    Abstract: A semiconductor device package includes a magnetically permeable layer having a top surface and a bottom surface opposite to the top surface. The semiconductor device package further includes a first conductive element in the magnetically permeable layer. The semiconductor device package further includes a first conductive via extending from the top surface of the magnetically permeable layer into the magnetically permeable layer to be electrically connected to the first conductive element. The first conductive via is separated from the magnetically permeable layer. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsing Kuo TIEN, Chih Cheng LEE
  • Publication number: 20210035896
    Abstract: A wiring structure includes an upper conductive structure, a lower conductive structure and an intermediate layer. The upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure and bonds the upper conductive structure and the lower conductive structure together. The upper conductive structure is electrically connected to the lower conductive structure. The intermediate layer includes a plurality of sub-layers. Each of the sub-layers is formed from a polymeric material. A boundary is formed between two adjacent sub-layers.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen Hung HUANG
  • Publication number: 20210035794
    Abstract: A semiconductor device package includes a first semiconductor device, a first redistribution layer (RDL) structure and a second RDL structure. The first semiconductor device has a first conductive terminal and a second conductive terminal. The first RDL structure covers the first conductive terminal. The second RDL structure covers the second conductive terminal and being separated from the first RDL structure.
    Type: Application
    Filed: August 1, 2019
    Publication date: February 4, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Pei-Jen LO, Cheng-Lung SHE