Patents Assigned to Advanced Semiconductor Engineering, Inc.
  • Publication number: 20260284905
    Abstract: The present disclosure provides an electronic device. The electronic device includes a sensor and a bionic structure. The sensor is configured to detect an object and to generate a sensing signal. The bionic structure includes a plurality of contact surfaces. The bionic structure is configured to select one of the plurality of contact surfaces to contact the object in response to the sensing signal from the sensor.
    Type: Application
    Filed: March 20, 2025
    Publication date: September 24, 2026
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Tseng Yu HUANG
  • Publication number: 20260293764
    Abstract: A semiconductor device package and a method of manufacturing the same are provided. The semiconductor device package includes a first circuit layer, a second circuit layer under the first circuit layer, a first electronic component between the first circuit layer and the second circuit layer and connected to the first circuit layer and a sub-package between the first circuit layer and the second circuit layer and connected to the second circuit layer. The sub package comprises a second electronic component under the first electronic component and a conductive structure configured to dissipate heat generated from the first electronic component.
    Type: Application
    Filed: April 7, 2026
    Publication date: September 24, 2026
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wei-Hao CHANG
  • Publication number: 20260287747
    Abstract: The present disclosure relates to an electronic device. The electronic device includes a first sensing element and a second sensing element. The first sensing element is configured to detect a distance to an object to be grabbed on a first scale. The second sensing element is configured to detect the distance to the object on a second scale. A precision of the second scale is different than that of the first scale.
    Type: Application
    Filed: March 20, 2025
    Publication date: September 24, 2026
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wei-Zhen QIU
  • Publication number: 20260292966
    Abstract: An electronic device and method of manufacturing the same are provided. The electronic device includes a carrier and an electronic component. The carrier includes a first conductive layer, wherein the first conductive layer includes a non-nanotwin copper layer and has an average grain size equal to or less than about 150 nm. The electronic component includes a pad electrically connected to the first conductive layer. The pad of the electronic component and the first conductive layer define a copper-to-copper bond.
    Type: Application
    Filed: December 31, 2025
    Publication date: September 24, 2026
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Po-Ming LEE, Erh-Ju LIN, Lu-Ming LAI
  • Publication number: 20260292977
    Abstract: An electronic device and method of manufacturing the same are provided. The electronic device includes a carrier, a conductive layer over the carrier, and an optical component. The optical component includes an electrode bonded to the conductive layer. An average grain size of the electrode is greater than an average grain size of the conductive layer.
    Type: Application
    Filed: December 31, 2025
    Publication date: September 24, 2026
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Po-Ming LEE, Erh-Ju LIN, Lu-Ming LAI
  • Publication number: 20260292978
    Abstract: An electronic device and method of manufacturing the same are provided. The electronic device includes a carrier, a first conductive layer, and a cover. The carrier has a first upper surface and a second upper surface at an elevation higher than that of the first upper surface. The first conductive layer is disposed over the second upper surface. The cover is disposed over the first conductive layer. The carrier, the first conductive layer, and the cover define a hermetic space. The first conductive layer includes a non-nanotwin copper layer and has an average grain size equal to or less than about 150 nm.
    Type: Application
    Filed: December 31, 2025
    Publication date: September 24, 2026
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Po-Ming LEE, Erh-Ju LIN, Lu-Ming LAI
  • Publication number: 20260276465
    Abstract: The present disclosure provides a bionic mechanical sensor. The bionic mechanical sensor includes a first rotatable region, a second rotatable region, an encapsulant, a plurality of sensors, and a conductive element. The encapsulant covers the first rotatable region and the second rotatable region and is exposed to an external environment. The plurality of sensors are within the first rotatable region and the second rotatable region. The conductive element is electrically connected to the plurality of sensors and embedded within the encapsulant.
    Type: Application
    Filed: March 14, 2025
    Publication date: September 17, 2026
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Chun-Kai CHANG
  • Publication number: 20260282934
    Abstract: The present disclosure relates to an electronic device. The electronic device includes a substrate and a chip antenna disposed over the substrate at a first elevation with respect to the substrate. The first elevation is greater than a thickness of the chip antenna. The chip antenna is configured to radiate a first signal through a first electrical path.
    Type: Application
    Filed: March 17, 2025
    Publication date: September 17, 2026
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yuanhao YU, Wei Shuen KAO
  • Publication number: 20260282972
    Abstract: An electronic device is provided. The electronic device includes a carrier and a protection layer. The carrier has a predetermined region and includes a pad disposed in the predetermined region. The protection layer is disposed over the carrier and defines the predetermined region. The protection layer is configured to block an encapsulation layer from covering the pad.
    Type: Application
    Filed: May 8, 2026
    Publication date: September 17, 2026
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chun-Kai CHANG, Hao-Chih HSIEH, Chao Wei LIU
  • Patent number: 12740422
    Abstract: The present disclosure provides an electronic device. The electronic device includes a first interposer, a first interconnection array, a first shielding wall, and a second interconnection array. The first interconnection array is disposed in the first interposer and electrically connected to ground. The first shielding wall continuously extends at a side of the first interconnection array. The second interconnection array is disposed between the first shielding wall and the first interconnection array. The second interconnection array is configured to transmit a signal.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: September 15, 2026
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsin-Yu Chen, Huei-Shyong Cho, Shih-Wen Lu
  • Publication number: 20260269455
    Abstract: The present disclosure provides an electronic device. The electronic device includes a carrier, a connector structure, and a first antenna structure. The carrier has a first surface and a second surface opposite to the first surface. The connector structure is disposed over the second surface of the carrier and defines at least one first recess configured to accommodate an external device. The first antenna structure is in directly contact with the connector structure.
    Type: Application
    Filed: March 7, 2025
    Publication date: September 10, 2026
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yuanhao YU, Wei Shuen KAO
  • Publication number: 20260271754
    Abstract: A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate includes a dielectric layer, a circuit layer, a first protection layer and a plurality of conductive posts. The dielectric layer has a first surface and a second surface that are opposite to each other. The circuit layer is embedded in the dielectric layer and is exposed from the first surface. The first protection layer covers a portion of the first circuit layer and defines a plurality of holes that expose a remaining portion of the first circuit layer. The conductive posts are formed in the holes.
    Type: Application
    Filed: April 27, 2026
    Publication date: September 10, 2026
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chun-Che LEE, Ming-Chiang LEE, Yuan-Chang SU, Tien-Szu CHEN, Chih-Cheng LEE, You-Lung YEN
  • Patent number: 12733524
    Abstract: An electronic device is provided. The electronic device includes a substrate, a first pad, and a second pad. The substrate defines a trench extending along a first direction. The first pad is disposed adjacent to the trench. The second pad is disposed next to the first pad. The first pad and the second pad are disposed at a same side of the trench and are arranged along the first direction. The first pad and the second pad define a first gap and a second gap therebetween along the first direction. The first gap is closer to the trench than the second gap is. A width of the first gap along the first direction is greater than a width of the second gap along the first direction.
    Type: Grant
    Filed: March 29, 2024
    Date of Patent: September 8, 2026
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chung Ju Yu, Shao Lun Yang, Tsung-Wei Lu
  • Patent number: 12733501
    Abstract: A semiconductor device package and a method of manufacturing the same are provided. The semiconductor device package includes a first carrier, a second carrier disposed over the first carrier, and a reinforcement connected to the second carrier and configured to prevent the second carrier from being recessed toward the first carrier.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: September 8, 2026
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Wei-Hao Chang
  • Patent number: 12733503
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a substrate having a first surface, an electrical contact disposed over a first region of the substrate, and an EMI shielding layer disposed over the substrate. The EMI shielding layer includes a non-uniform thickness and an elevation of the EMI shielding layer is higher than an elevation of the electrical contact with respect to the first surface of the substrate. A method for manufacturing a semiconductor device package is also disclosed.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: September 8, 2026
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Zheng Wei Wu, Cheng Kai Chang
  • Publication number: 20260262515
    Abstract: An electronic device includes a first electronic component, an encapsulant and a second electronic component. The encapsulant encapsulates the first electronic component. The second electronic component is disposed over the first electronic component and separated from the encapsulant. The second electronic component is configured to receive a power from the first electronic component.
    Type: Application
    Filed: April 20, 2026
    Publication date: September 3, 2026
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Yuan KUNG, Hung-Yi LIN
  • Publication number: 20260262502
    Abstract: An electronic device and a method for manufacturing the same are provided. The electronic device includes a substrate, an encapsulant and an electronic component. The encapsulant is disposed over the substrate, and has a first top surface, a second top surface and a first lateral surface extending between the first top surface and the second top surface. A roughness of the first lateral surface is less than or equal to a roughness of the second top surface. The electronic component is disposed over the second top surface of the encapsulant and electrically connected to the substrate.
    Type: Application
    Filed: April 27, 2026
    Publication date: September 3, 2026
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chih-Hsin LAI, Chih-Cheng LEE, Shao-Lun YANG, Wei-Chih CHO
  • Publication number: 20260256013
    Abstract: The present disclosure provides a method of manufacturing an electronic device. The method includes providing a panel assembly including a plurality of first electronic components, dividing the panel assembly into a plurality of strips, forming a first encapsulant over one of the plurality of strips, and dividing the one of the plurality of strips into a plurality of electronic devices.
    Type: Application
    Filed: February 26, 2025
    Publication date: August 27, 2026
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ping-Feng YANG, Chia-Hao SUNG, Chao-Hung WENG, Chun Hung TSAI, Kuan-Lin YEH, Shang HSU, Pei-Chin HUANG, Ling-Hua Wang
  • Publication number: 20260255984
    Abstract: An electronic device is provided. The electronic device includes a circuit pattern layer. The circuit pattern layer includes a first surface, a second surface recessed with respect to the first surface; and a third surface recessed with respect to the first surface and adjacent to and spaced apart from the second surface. The second surface and the third surface are mis-aligned with each other.
    Type: Application
    Filed: April 17, 2026
    Publication date: August 27, 2026
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Hui-Chen HSU
  • Publication number: 20260255992
    Abstract: A wiring structure and a method for manufacturing the same are provided. The wiring structure includes a conductive structure, an intermediate structure and a seed layer. The conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The conductive structure defines an accommodating hole. The intermediate structure is bonded to an inner surface of the accommodating hole. The seed layer is bonded to the accommodating hole through the intermediate structure.
    Type: Application
    Filed: April 17, 2026
    Publication date: August 27, 2026
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen Hung HUANG