Patents Assigned to Advanced Semiconductor Engineering, Inc.
  • Publication number: 20250149457
    Abstract: The present disclosure relates to an electronic device that includes a first electronic component, a second electronic component, an interconnection structure below the first electronic component and the second electronic component and electrically connecting the first electronic component to the second electronic component, and a first waveguide below the first electronic component and the second electronic component and configured to transmit electromagnetic waves.
    Type: Application
    Filed: November 2, 2023
    Publication date: May 8, 2025
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Yu HO, Hong-Sheng HUANG, Sheng-Chi HSIEH, Shao-En HSU, Huei-Shyong CHO
  • Publication number: 20250149396
    Abstract: A package structure is provided. The package structure includes a substrate, a first electronic component, a first electrical connector, and a protective layer. The first electronic component is over the substrate. The first electrical connector is between the substrate and the first electronic component. The protective layer encapsulates the first electrical connector. The protective layer has a first curved lateral surface concave toward the first electrical connector and recessed with respect to a lateral surface of the first electronic component.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 8, 2025
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Po-Jen CHENG, Wei-Jen WANG, Wei-Long CHEN, Hao-Chung WANG, Kai-Wen CHAN
  • Publication number: 20250134456
    Abstract: A wearable device is provided. The wearable device includes an electronic component and an encapsulant. The encapsulant includes a low-penetrability region encapsulating the electronic component and a high-penetrability region physically separated from the electronic component.
    Type: Application
    Filed: January 7, 2025
    Publication date: May 1, 2025
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Chang-Lin YEH
  • Publication number: 20250133662
    Abstract: The present disclosure provides an electronic device and method of manufacturing the same. The electronic device includes a first region, a second region, an electronic component, and a first sensing element. The second region is adjacent to the first region. The first region has a first pliability. The second region has a second pliability. The second pliability is greater than the first pliability. The electronic component is disposed at the first region. The first sensing element is disposed at the second region and electrically connected to the electronic component.
    Type: Application
    Filed: December 31, 2024
    Publication date: April 24, 2025
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tun-Ching PI, Ming-Hung CHEN
  • Publication number: 20250132261
    Abstract: A semiconductor device package and a method of manufacturing the same are provided. The semiconductor device package includes a first carrier, an encapsulant, a second carrier and one or more supporters. The first carrier has a first surface and a first side contiguous with the first surface. The encapsulant is on the first surface of the first carrier, and the first side of the first carrier is exposed from the encapsulant. The second carrier is disposed over the first carrier. The one or more supporters are spaced apart from the first side of the first carrier and connected between the first carrier and the second carrier. The one or more supporters are arranged asymmetrically with respect to the geographic center of the first carrier. The one or more supporters are fully sealed in the encapsulant.
    Type: Application
    Filed: December 24, 2024
    Publication date: April 24, 2025
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Chao Wei LIU
  • Publication number: 20250132232
    Abstract: An electronic device is provided. The electronic device includes a first circuit structure, a second circuit structure, a conductive layer, and a supporting structure. The conductive layer is disposed between the first circuit structure and the second circuit structure.
    Type: Application
    Filed: October 19, 2023
    Publication date: April 24, 2025
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Jen-Hao PAN
  • Publication number: 20250133322
    Abstract: The present disclosure provides a wearable component. The wearable component includes a first carrier and a first electronic component at least partially embedded within the first carrier. The first carrier and the first electronic component define a space configured for audio transmission. An ear tip and a method of manufacturing a wearable component are also provided.
    Type: Application
    Filed: December 30, 2024
    Publication date: April 24, 2025
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chang Yi WU, Hung Yi LIN, Jenchun CHEN
  • Publication number: 20250132278
    Abstract: An electronic device is disclosed. The electronic device includes a unit chip. The unit chip includes an electronic component having a power delivery circuit and a reinforcement supporting the electronic component. The reinforcement is configured to transmit a power signal to the power delivery circuit. The reinforcement includes a thermosetting reinforcement or a glass reinforcement.
    Type: Application
    Filed: October 20, 2023
    Publication date: April 24, 2025
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chih-Jing HSU, Hsu-Nan FANG
  • Patent number: 12283537
    Abstract: An electronic package is provided in the present disclosure. The electronic package comprises: a heat spreading component; a first electronic component disposed on the heat spreading component; and a second electronic component disposed on the first electronic component, wherein the second electronic component comprises an interconnection structure passing through the second electronic component and electrically connecting the first electronic component. In this way, through the use of the interconnection structure, the heat dissipation of the electronic components in the package can be improved. Also, through the use of the encapsulant, the stacked electronic components can be protected by the encapsulant so as to avoid being damaged.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: April 22, 2025
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: You-Lung Yen, Bernd Karl Appelt
  • Patent number: 12283585
    Abstract: An optoelectronic device package includes a first redistribution layer (RDL), a first electronic die disposed over the first RDL, wherein an active surface of the first electronic die faces the first RDL. The optoelectronic device package further includes a second electronic die disposed over the first RDL, and a photonic die disposed over and electrically connected to the second electronic die. An active surface of the second electronic die is opposite to the first RDL.
    Type: Grant
    Filed: February 6, 2024
    Date of Patent: April 22, 2025
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Chi-Han Chen
  • Patent number: 12283569
    Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a first substrate with a first surface and a second surface opposite to the first surface, a second substrate adjacent to the first surface of the first substrate, and an encapsulant encapsulating the first substrate and the second substrate. The first substrate defines a space. The second substrate covers the space. The second surface of the first substrate is exposed by the encapsulant. A surface of the encapsulant is coplanar with the second surface of the first substrate or protrudes beyond the second surface of the first substrate.
    Type: Grant
    Filed: February 21, 2023
    Date of Patent: April 22, 2025
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yung-Hsing Chang, Wen-Hsin Lin
  • Publication number: 20250125209
    Abstract: A semiconductor package structure includes a circuit pattern structure, an encapsulant and an anchoring structure. The encapsulant is disposed on the circuit pattern structure. The anchoring structure is disposed adjacent to an interface between the encapsulant and the circuit pattern structure, and is configured to reduce a difference between a variation of expansion of the encapsulant and a variation of expansion of the circuit pattern structure in an environment of temperature variation.
    Type: Application
    Filed: December 23, 2024
    Publication date: April 17, 2025
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yung-Shun CHANG, Teck-Chong LEE
  • Publication number: 20250115473
    Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a substrate with a first groove and a semiconductor device. The first groove has a first portion, a second portion, and a third portion, and the second portion is between the first portion and the third portion. The semiconductor device includes a membrane and is disposed on the second portion of the first groove. The semiconductor device has a first surface adjacent to the substrate and opposite to the membrane. The membrane is exposed by the first surface.
    Type: Application
    Filed: December 17, 2024
    Publication date: April 10, 2025
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Liang HSIAO, Lu-Ming LAI, Ching-Han HUANG, Chia-Hung SHEN
  • Patent number: 12272766
    Abstract: A semiconductor device package includes a carrier, an emitting element and a first package body. The carrier includes a first surface and a second surface opposite to the first surface. The emitting element is disposed on the first surface of the carrier. The first package body is disposed over the first surface of the carrier and spaced apart from the first surface of the carrier.
    Type: Grant
    Filed: February 28, 2023
    Date of Patent: April 8, 2025
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tang-Yuan Chen, Meng-Wei Hsieh, Cheng-Yuan Kung
  • Patent number: 12272687
    Abstract: A semiconductor device package includes a redistribution layer, a plurality of conductive pillars, a reinforcing layer and an encapsulant. The conductive pillars are in direct contact with the first redistribution layer. The reinforcing layer surrounds a lateral surface of the conductive pillars. The encapsulant encapsulates the first redistribution layer and the reinforcing layer. The conductive pillars are separated from each other by the reinforcing layer.
    Type: Grant
    Filed: December 6, 2022
    Date of Patent: April 8, 2025
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ya Fang Chan, Yuan-Feng Chiang
  • Patent number: 12272671
    Abstract: A semiconductor device includes: a substrate having a first surface and a second surface opposite to the first surface; an electronic component disposed on the first surface of the substrate; a sensor disposed adjacent to the second surface of the substrate; an electrical contact disposed on the first surface of the substrate; and a package body exposing a portion of the electrical contact.
    Type: Grant
    Filed: June 20, 2023
    Date of Patent: April 8, 2025
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chih-Ming Hung, Meng-Jen Wang, Tsung-Yueh Tsai, Jen-Kai Ou
  • Patent number: 12266610
    Abstract: A semiconductor package device and a method of manufacturing a semiconductor package device are provided. The semiconductor package device includes a substrate, a first electronic component, a first dielectric layer, and a first hole. The substrate has a first surface and a second surface opposite to the first surface. The first electronic component is disposed on the first surface. The first dielectric layer is disposed on the second surface and has a third surface away from the substrate. The first hole extends from the first dielectric layer and the substrate. The first hole is substantially aligned with the first electronic component.
    Type: Grant
    Filed: September 12, 2022
    Date of Patent: April 1, 2025
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yencheng Kuo, Shao-Lun Yang
  • Patent number: 12266632
    Abstract: A package structure includes: 1) a circuit substrate; 2) a first semiconductor device disposed on the circuit substrate; 3) a first insulation layer covering a sidewall of the first semiconductor device; 4) a second insulation layer covering the first insulation layer; and 5) a third insulation layer disposed on the circuit substrate and in contact with the second insulation layer.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: April 1, 2025
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chi-Chih Shen, Jen-Chuan Chen, Tommy Pan
  • Patent number: 12267961
    Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.
    Type: Grant
    Filed: January 23, 2024
    Date of Patent: April 1, 2025
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Fan Chen, Chien-Hao Wang
  • Patent number: 12266644
    Abstract: A semiconductor device package includes a first semiconductor device having a first surface, an interconnection element having a surface substantially coplanar with the first surface of the first semiconductor device, a first encapsulant encapsulating the first semiconductor device and the interconnection element, and a second semiconductor device disposed on and across the first semiconductor device and the interconnection element.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: April 1, 2025
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chang-Yu Lin, Chi-Han Chen, Chieh-Chen Fu