Patents Assigned to Advanced Semiconductor Engineering, Inc.
  • Publication number: 20190355664
    Abstract: An electronic device includes a first substrate, a first conductor, a first insulation layer, a second substrate, a second conductor, a second insulation layer. The first substrate has a first surface. The first conductor is disposed on the first surface of the first substrate. The first insulation layer is on the first conductor. The second substrate has a second surface facing toward the first surface of the first substrate. The second conductor is disposed on the second surface of the second substrate. The second insulation layer is on the second conductor. The first insulation layer is in contact with a sidewall of the second conductor. The second insulation layer is in contact with a sidewall of the first conductor. A coefficient of thermal expansion (CTE) of the first insulation layer is greater than a CTE of the first conductor.
    Type: Application
    Filed: May 21, 2018
    Publication date: November 21, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen-Long LU
  • Publication number: 20190355676
    Abstract: A semiconductor device package includes a substrate, a first coil, a dielectric layer and a second coil. The first coil is disposed on the substrate. The first coil includes a first conductive segment and a second conductive segment. The dielectric layer covers the first conductive segment of the first coil and the second conductive segment of the first coil and defines a first recess between the first conductive segment of the first coil and the second conductive segment of the first coil. The second coil is disposed on the dielectric layer. The second coil has a first conductive segment disposed within the first recess.
    Type: Application
    Filed: May 17, 2018
    Publication date: November 21, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shun-Tsat TU, Pei-Jen LO, Yan-Si LIN, Chien-Chi KUO
  • Patent number: 10483196
    Abstract: A substrate structure includes a carrier, a first metal layer, a circuit layer and a dielectric layer. The carrier has a first surface and a second surface. The first metal layer is disposed on the first surface of the carrier. The circuit layer is disposed on the first metal layer. The dielectric layer covers the circuit layer and defines a plurality of openings to expose portions of the circuit layer and portions of the first metal layer.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: November 19, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Yu-Ying Lee
  • Patent number: 10483254
    Abstract: An electronic module includes a first sub-module and a second sub-module. The first sub-module includes a first substrate, a first electronic component disposed on the first substrate and a first electrode. The second sub-module includes a second substrate, a second electronic component disposed on the second substrate and a second electrode spaced from the first electrode. The second electrode faces the first electrode to form a capacitor for transmitting an alternating current (AC) signal between the first sub-module and the second sub-module.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: November 19, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Chang-Lin Yeh
  • Publication number: 20190346305
    Abstract: An optical system and a method of manufacturing an optical system are provided. The optical system includes a carrier, a light emitter, a light receiver, a block structure and an encapsulant. The light emitter is disposed on the carrier. The light receiver is disposed on the carrier and physically spaced apart from the light emitter. The light receiver has a light detecting area. The block structure is disposed on the carrier. The encapsulant is disposed on the carrier and covers the light emitter, the light receiver and the block structure. The encapsulant has a recess over the block structure.
    Type: Application
    Filed: May 7, 2019
    Publication date: November 14, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsin-Ying HO, Ying-Chung CHEN
  • Publication number: 20190348385
    Abstract: An electronic device includes a first dielectric layer, a second dielectric layer and at least one first stud bump. The second dielectric layer is disposed on the first dielectric layer. The first stud bump is disposed in the first dielectric layer and the second dielectric layer. The first stud bump includes a bump portion and a stud portion, and the stud portion is disposed on the bump portion.
    Type: Application
    Filed: May 8, 2018
    Publication date: November 14, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen-Long LU
  • Publication number: 20190348344
    Abstract: A connection structure is provided. The connection structure includes an intermediate conductive layer, a first conductive layer and a second conductive layer. The intermediate conductive layer includes a first surface and a second surface opposite to the first surface. The intermediate conductive layer has a first coefficient of thermal expansion. The first conductive layer is in contact with the first surface of the intermediate conductive layer. The first conductive layer has a second CTE. The second conductive layer is in contact with the second surface of the intermediate conductive layer. The first conductive layer and the second conductive layer are formed of the same material. One of the first CTE and the second CTE is negative, and the other is positive.
    Type: Application
    Filed: May 8, 2018
    Publication date: November 14, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen-Long LU, Jen-Kuang FANG
  • Publication number: 20190348351
    Abstract: A semiconductor substrate and a method of manufacturing the same are provided. The semiconductor substrate includes a carrier and a conductive post. The carrier has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The carrier has a through hole extending between the first surface and the second surface. The carrier has a first opening on the lateral surface. The conductive post is disposed within the through hole.
    Type: Application
    Filed: May 11, 2018
    Publication date: November 14, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tsann Huei LEE, Lu-Ming LAI
  • Publication number: 20190348371
    Abstract: A semiconductor package includes a semiconductor die, a plurality of conductive bumps, a shielding layer, an encapsulant and a redistribution layer. The semiconductor die has an active surface, a backside surface and a lateral surface. The conductive bumps are disposed on the active surface of the semiconductor die. The shielding layer is disposed on the lateral surface of the semiconductor die. The encapsulant covers the shielding layer, and has a first surface and a second surface opposite to the first surface. The redistribution layer is disposed on the first surface of the encapsulant and electrically connected to the semiconductor die through the conductive bumps. The shielding layer is electrically connected to the redistribution layer.
    Type: Application
    Filed: May 11, 2018
    Publication date: November 14, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Nan FANG, Chun-Jun ZHUANG, Yung I. YEH
  • Publication number: 20190348352
    Abstract: A wiring structure includes an insulating layer and a conductive structure. The insulating layer has an upper surface and a lower surface opposite to the upper surface, and defines an opening extending through the insulating layer. The conductive structure is disposed in the opening of the insulating layer, and includes a first barrier layer and a wetting layer. The first barrier layer is disposed on a sidewall of the opening of the insulating layer, and defines a through hole extending through the first barrier layer. The wetting layer is disposed on the first barrier layer. A portion of the wetting layer is exposed from the through hole of the first barrier layer and the lower surface of the insulating layer to form a ball pad.
    Type: Application
    Filed: May 8, 2018
    Publication date: November 14, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung HUANG, Chien-Mei HUANG, Yan Wen CHUNG
  • Publication number: 20190348354
    Abstract: A substrate includes a first dielectric layer having a first surface and a second dielectric layer having a first surface disposed adjacent to the first surface of the first dielectric layer. The substrate further includes a first conductive via disposed in the first dielectric layer and having a first end adjacent to the first surface of the first dielectric layer and a second end opposite the first end. The substrate further includes a second conductive via disposed in the second dielectric layer and having a first end adjacent to the first surface of the second dielectric layer. A width of the first end of the first conductive via is smaller than a width of the second end of the first conductive via, and a width of the first end of the second conductive via is smaller than the width of the first end of the first conductive via.
    Type: Application
    Filed: May 10, 2018
    Publication date: November 14, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Lin HO, Chih-Cheng LEE
  • Patent number: 10475775
    Abstract: A semiconductor package device comprises a circuit layer, an electronic component disposed on the circuit layer, a package element and a first encapsulant. The package element is disposed on the circuit layer. The package element includes at least two electrical contacts electrically connected to the circuit layer. The first encapsulant is disposed on the circuit layer. The first encapsulant encapsulates the electronic component and the package element and exposes the electrical contacts of the package element.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: November 12, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chun-Jun Zhuang
  • Patent number: 10475734
    Abstract: A semiconductor device package includes: (1) a substrate having a first surface and a second surface opposite to the first surface; (2) a first patterned conductive layer on the first surface of the substrate and having a first surface and a second surface, wherein the second surface of the first patterned conductive layer is adjacent to the substrate and opposite to the first surface of the first patterned conductive layer; (3) a first insulation layer on the first surface of the substrate and having a first surface and a second surface, wherein the second surface of the first insulation layer is adjacent to the substrate and opposite to the first surface of the first insulation layer; and (4) a second patterned conductive layer extending from the first surface of the first insulation layer to the second surface of the substrate, the second patterned conductive layer electrically connected to the first patterned conductive layer.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: November 12, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Hua Chen, Sheng-Chi Hsieh, Cheng-Yuan Kung
  • Patent number: 10475718
    Abstract: A semiconductor device package includes a dielectric layer, a first RDL, a second RDL, an inductor, a first electronic component and a second electronic component. The first RDL is adjacent to a first surface of the dielectric layer, and the first RDL includes first conductive pieces. The second RDL is adjacent to a second surface of the dielectric layer, and the second RDL includes second conductive pieces. The inductor is disposed in the dielectric layer. The inductor includes induction pillars, wherein each of the induction pillars is disposed through the dielectric layer, and each of the induction pillars is interconnected between a respective one of the first conductive pieces of the first RDL and a respective one of the second conductive pieces of the second RDL. The first electronic component and the second electronic component are between the first RDL and the second RDL, and electrically connected to each other through the inductor.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: November 12, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Hua Chen, Hung-Yi Lin, Cheng-Yuan Kung, Teck-Chong Lee, Shiuan-Yu Lin
  • Patent number: 10472228
    Abstract: A Micro Electro-Mechanical System (MEMS) device package includes a first circuit layer, a partition wall, a MEMS component, a second circuit layer and a polymeric dielectric layer. The partition wall is disposed over the first circuit layer. The MEMS component is disposed over the partition wall and electrically connected to the first circuit layer. The first circuit layer, the partition wall and the MEMS component enclose a space. The second circuit layer is disposed over and electrically connected to the first circuit layer. The polymeric dielectric layer is disposed between the first circuit layer and the second circuit layer.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: November 12, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Hua Chen, Cheng-Yuan Kung, Che-Hau Huang, Chin-Cheng Kuo
  • Publication number: 20190341505
    Abstract: A semiconductor device package includes a substrate, a first encapsulant and a second encapsulant. The substrate has an optical region and a surface-mount technology (SMT) device region. The first encapsulant includes a first portion disposed on the optical region and covers the optical region and a second portion disposed on the SMT device region and covers the SMT device region. The second encapsulant is disposed on the substrate and covers at least a portion of the second portion of the first encapsulant and a portion of the first portion of the first encapsulant.
    Type: Application
    Filed: May 3, 2018
    Publication date: November 7, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Chanyuan LIU
  • Publication number: 20190341368
    Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a substrate, an interposer disposed on the substrate, a conductive pillar disposed on the substrate, a first semiconductor device disposed on the interposer and electrically connected to the conductive pillar, a second semiconductor device disposed on the interposer, and an encapsulant surrounding the conductive pillar. The first semiconductor device includes a first conductive pad electrically connected to the interposer. The second semiconductor device includes a second conductive pad electrically connected to the interposer.
    Type: Application
    Filed: May 1, 2018
    Publication date: November 7, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ian HU, Ming-Han WANG, Tsun-Lung Hsieh, Chih-Yi HUANG, Chih-Pin HUNG
  • Patent number: 10468340
    Abstract: The present disclosure relates to a wiring structure and a semiconductor package. The wiring structure comprises a first wiring pattern, a dielectric layer and a dummy structure. The first wiring pattern includes a conductive land having a width W1 and a surface area A, and a conductive trace having a width W2 and electrically connected to the conductive land, wherein ((W1*W2)/A)*100%? about 25%. The dielectric layer covers the first wiring pattern, and the dummy structure is adjacent to the conductive trace.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: November 5, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Yan Wen Chung, Wei Chu Sun
  • Patent number: 10461005
    Abstract: A semiconductor package includes a dielectric layer and a conductive post. The dielectric layer has a first surface and a second surface opposite to the first surface. The conductive post is disposed in the dielectric layer. The conductive post includes a first portion and a second portion disposed above the first portion. The second portion of the conductive post is recessed from the second surface of the dielectric layer.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: October 29, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Publication number: 20190326256
    Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a first substrate with a first surface and a second surface opposite to the first surface, a second substrate adjacent to the first surface of the first substrate, and an encapsulant encapsulating the first substrate and the second substrate. The first substrate defines a space. The second substrate covers the space. The second surface of the first substrate is exposed by the encapsulant. A surface of the encapsulant is coplanar with the second surface of the first substrate or protrudes beyond the second surface of the first substrate.
    Type: Application
    Filed: April 23, 2018
    Publication date: October 24, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yung-Hsing CHANG, Wen-Hsin LIN