Patents Assigned to Advanced Semiconductor Engineering, Inc.
  • Patent number: 10910329
    Abstract: The disclosure relates to a semiconductor package device. The semiconductor package device includes a substrate, a waveguide component, a package body, a first dielectric layer, an antenna pattern, and an antenna feeding layer. The waveguide component is on the substrate. The package body is on the substrate and encapsulates the waveguide component. The first dielectric layer is on the package body and has a first surface and a second surface adjacent to the package body and opposite to the first surface. The antenna pattern is on the first surface of the first dielectric layer. The antenna feeding layer is on the second surface of the first dielectric layer.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: February 2, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Kuo-Hsien Liao, Alex Chi-Hong Chan
  • Patent number: 10910507
    Abstract: A semiconductor package device comprises a substrate, a light emitter, a light detector and a transparent conductive film. The substrate as a first surface and a second surface opposite to the first surface. The light emitter is disposed on the first surface of the substrate and has a light emission area adjacent to the first surface of the substrate. The light detector is disposed on the first surface of the substrate and has a light receiving area adjacent to the first surface of the substrate. The transparent conducting film is disposed on the second surface of the substrate.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: February 2, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Ling Huang, Ying-Chung Chen
  • Patent number: 10910233
    Abstract: A semiconductor device package includes a substrate and a monolithic encapsulant. The substrate has a first surface, a second surface opposite to the first surface and a plurality of lateral surfaces extending between the first surface and the second surface. The substrate defines a first opening and a second opening that extend between the first surface and the second surface and respectively expose the plurality of lateral surfaces. The monolithic encapsulant includes a first portion disposed on the first surface of the substrate, a second portion disposed on the second surface of the substrate and a third portion disposed within the first opening and the second opening.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: February 2, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Chanyuan Liu
  • Publication number: 20210028144
    Abstract: A semiconductor device package includes a first substrate having a first surface, a first electrical contact disposed on the first surface of the first substrate, a second substrate having a second surface facing the first surface of the first substrate, and a second electrical contact disposed on the second surface of the second substrate. The first electrical contact has a base portion and a protrusion portion. The second electrical contact covers at least a portion of the protrusion portion of the first electrical contact. The second electrical contact has a first surface facing the first substrate and a second surface facing the second substrate.
    Type: Application
    Filed: July 24, 2019
    Publication date: January 28, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen-Long LU
  • Publication number: 20210028134
    Abstract: A semiconductor package structure and a method of manufacturing the semiconductor package structure are disclosed. The semiconductor package structure includes a first semiconductor device having an active surface, a redistribution structure in electrical connection with the first semiconductor device, and a second semiconductor device bonded to the active surface of the first semiconductor device, and disposed between the first semiconductor device and the redistribution structure.
    Type: Application
    Filed: July 23, 2020
    Publication date: January 28, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Mark GERBER
  • Publication number: 20210028150
    Abstract: A semiconductor device package includes a substrate, a stacked structure and an encapsulation layer. The substrate includes a circuit layer, a first surface and a second surface opposite to the first surface. The substrate defines at least one cavity through the substrate. The stacked structure includes a first semiconductor die disposed on the first surface and electrically connected on the circuit layer, and at least one second semiconductor die stacked on the first semiconductor die and electrically connected to the first semiconductor die. The second semiconductor die is at least partially inserted into the cavity. The encapsulation layer is disposed in the cavity and at least entirely encapsulating the second semiconductor die.
    Type: Application
    Filed: July 26, 2019
    Publication date: January 28, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: You-Lung YEN, Bernd Karl APPELT, Kay Stefan ESSIG
  • Patent number: 10903152
    Abstract: A substrate includes: (1) a first patterned conductive layer, the first patterned conductive layer including a pair of first transmission lines adjacent to each other; and (2) a first reference layer above the pair of first transmission lines, the first reference layer defining an opening, wherein the pair of first transmission lines are exposed to the opening.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: January 26, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yuan-Hsi Chou, Tsun-Lung Hsieh, Chen-Chao Wang
  • Patent number: 10903169
    Abstract: A conductive structure includes a core portion, a plurality of electronic devices and a filling material. The core portion defines a cavity. The electronic devices are disposed in the cavity of the core portion. The filling material is disposed between the electronic devices and a sidewall of the cavity of the core portion.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: January 26, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Patent number: 10903151
    Abstract: A semiconductor substrate includes a dielectric layer, a first conductive layer, a first barrier layer and a conductive post. The dielectric layer has a first surface and a second surface opposite to the first surface. The first conductive layer is disposed adjacent to the first surface of the dielectric layer. The first barrier layer is disposed on the first conductive layer. The conductive post is disposed on the first barrier layer. A width of the conductive post is equal to or less than a width of the first barrier layer.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: January 26, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 10903907
    Abstract: A system including optical devices is provided. The system includes a first substrate and a first device for optical communication. The first device has a first surface, a second surface opposite to the first surface, and a first side contiguous with the first surface and the second surface. Moreover, the first side is smaller than one of the first surface and the second surface in terms of area. The first device is attached at the first side thereof to the first substrate.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: January 26, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chang-Yu Lin, Cheng-Yuan Kung, Hung-Yi Lin
  • Patent number: 10903561
    Abstract: A semiconductor device package includes a first glass carrier, a package body, a first circuit layer and a first antenna layer. The first circuit layer is disposed on the first surface of the first glass carrier. The first circuit layer has a redistribution layer (RDL). The package body is disposed on the first circuit layer. The package body has an interconnection structure penetrating the package body and is electrically connected to the RDL of the first circuit layer. The first antenna layer is disposed on the second surface of the first glass carrier.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: January 26, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Hua Chen, Sheng-Chi Hsieh, Chen-Chao Wang, Teck-Chong Lee
  • Publication number: 20210020594
    Abstract: A semiconductor package structure includes a base material, at least one semiconductor chip, an encapsulant, a depression structure, a redistribution layer and at least one conductive via. The semiconductor chip is disposed on the base material. The encapsulant is disposed on the base material and covers the at least one semiconductor chip. The encapsulant has an outer side surface. The depression structure is disposed adjacent to and exposed from of the outer side surface the encapsulant. The redistribution layer is disposed on the encapsulant. The conductive via is disposed in the encapsulant and electrically connects the semiconductor chip and the redistribution layer.
    Type: Application
    Filed: July 15, 2019
    Publication date: January 21, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chi-Tsung CHIU, Hui-Ying HSIEH, Hui Hua LEE, Cheng Yuan CHEN
  • Publication number: 20210020579
    Abstract: A semiconductor device package includes a substrate and an electronic component disposed on the substrate. The electronic component has an active surface facing away from the substrate. The substrate has a first conductive pad and a second conductive pad disposed thereon. The electronic component has a first electrical contact and a second electrical contact disposed on the active surface. The semiconductor device package further includes a first metal layer connecting the first electrical contact with the first conductive pad, a second metal layer connecting the second electrical contact with the second conductive pad, a first seed layer disposed below the first metal layer; and a first isolation layer disposed between the first metal layer and the second metal layer. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Application
    Filed: July 15, 2019
    Publication date: January 21, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen-Long LU
  • Publication number: 20210020533
    Abstract: A semiconductor device package includes an electronic component, an encapsulation layer encapsulating the electronic component, and a passivation layer stacking with the encapsulation layer. The passivation layer has a first surface facing the encapsulation layer, a second surface opposite to the first surface, and a first sidewall connecting the first surface and the second surface. The first sidewall inclines with respect to the second surface, and a first projection width of the encapsulation layer is greater than a second projection width of the passivation layer.
    Type: Application
    Filed: July 18, 2019
    Publication date: January 21, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen-Long LU
  • Publication number: 20210017018
    Abstract: A semiconductor package structure includes an electronic device having an exposed region adjacent to a first surface, a dam surrounding the exposed region of the semiconductor die and disposed on the first surface, the dam having a top surface away from the first surface, an encapsulant encapsulating the first surface of the electronic device, exposing the exposed region of the electronic device. A surface of the dam is retracted from a top surface of the encapsulant. A method for manufacturing the semiconductor package structure is also provided.
    Type: Application
    Filed: July 19, 2019
    Publication date: January 21, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wei-Wei LIU, Huei-Siang WONG, Lu-Ming LAI
  • Publication number: 20210020597
    Abstract: A semiconductor package structure includes a conductive structure, at least one semiconductor element, an encapsulant, a redistribution structure and a plurality of bonding wires. The semiconductor element is disposed on and electrically connected to the conductive structure. The encapsulant is disposed on the conductive structure to cover the semiconductor element. The redistribution structure is disposed on the encapsulant, and includes a redistribution layer. The bonding wires electrically connect the redistribution structure and the conductive structure.
    Type: Application
    Filed: July 17, 2019
    Publication date: January 21, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Wei CHANG, Shang-Wei YEH, Chung-Hsi WU, Min Lung HUANG
  • Publication number: 20210013118
    Abstract: A semiconductor package structure includes a package substrate, at least one semiconductor die, a heat dissipating device, at least one electronic device and a heat transmitting structure. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is electrically connected to the first surface of the package substrate. The heat dissipating device is thermally connected to the first surface of the package substrate. The electronic device is electrically connected to the second surface of the package substrate. The electronic device has a first surface and a second surface opposite to the first surface, and the first surface of the electronic device faces the second surface of the package substrate. The heat transmitting structure is disposed adjacent to the second surface of the package substrate, and thermally connected to the electronic device and the heat dissipating device.
    Type: Application
    Filed: July 10, 2019
    Publication date: January 14, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsin-En Chen, Ian Hu, Chih-Pin Hung
  • Publication number: 20210013585
    Abstract: A semiconductor device package includes a substrate and an antenna module. The substrate has a first surface and a second surface opposite to the first surface. The antenna module is disposed on the first surface of the substrate with a gap. The antenna module has a support and an antenna layer. The support has a first surface facing away from the substrate and a second surface facing the substrate. The antenna layer is disposed on the first surface of the support. The antenna layer has a first antenna pattern and a first dielectric layer.
    Type: Application
    Filed: July 9, 2019
    Publication date: January 14, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Lin Ho, Chih-Cheng Lee, Chun Chen Chen, Yuanhao Yu
  • Publication number: 20210013163
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes an antenna zone and a routing zone. The routing zone is disposed on the antenna zone, where the antenna zone includes a first insulation layer and two or more second insulation layer and a thickness of the first insulation layer is different from that of the second insulation layer.
    Type: Application
    Filed: July 10, 2019
    Publication date: January 14, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung HUANG, Yan Wen CHUNG, Wei Chu SUN
  • Publication number: 20210013375
    Abstract: A semiconductor device package includes a carrier, a conductive pillar, an adhesive layer and a package body. The conductive pillar is disposed on the carrier. The conductive pillar has a top surface facing away from the carrier. The adhesive layer is disposed on the top surface of the conductive pillar. The package body is disposed on the carrier. The package body has a top surface facing away from the carrier. The top surface has a first portion and a second portion. The first portion and the second portion of the top surface of the package body are discontinuous.
    Type: Application
    Filed: July 11, 2019
    Publication date: January 14, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Mei-Yi WU