Patents Assigned to Advanced Semiconductor Engineering
  • Patent number: 8728915
    Abstract: A wafer laser-marking method is provided. First, a wafer having a first surface (an active surface) and a second surface (a back surface) opposite to each other is provided. Next, the wafer is thinned. Then, the thinned wafer is fixed on a non-UV tape such that the second surface of the wafer is attached to the tape. Finally, the laser marking step is performed, such that a laser light penetrates the non-UV tape and marks a pattern on the second surface of the wafer. According to the laser-marking method of the embodiment, the pattern is formed by the non-UV residuals left on the second surface of the wafer, and the components of the glue residuals at least include elements of silicon and carbon.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: May 20, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Pin Tsai, Cheng-I Huang, Yao-Hui Hu
  • Patent number: 8720053
    Abstract: A process for fabricating a circuit board that includes a dielectric layer, a circuit layer, and an insulation layer. The circuit layer is disposed on the dielectric layer and has a pad region and a trace region. The insulation layer is disposed on the circuit layer and covers the trace region. Here, a thickness of the pad region is less than a thickness of the trace region.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: May 13, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Shih-Chang Lee, Kun-Ching Chen, Ming-Loung Lu, Chun-Che Lee
  • Publication number: 20140117388
    Abstract: Light-emitting semiconductor packages and related methods. The light-emitting semiconductor package includes a central barrier, a plurality of leads, a light-emitting device, a first encapsulant, a package body, and a second encapsulant. The light-emitting device is disposed in the interior space defined by the central barrier and is electrically connected to the leads surrounding the central barrier. The light-emitting device includes upper and lower light-emitting surfaces. The first encapsulant and the second encapsulant cover the upper and lower light-emitting surfaces, respectively. The package body encapsulates portions of the central barrier, portions of each of the leads, and the first encapsulant. The light-emitting semiconductor package can emit light from both the upper and lower sides thereof.
    Type: Application
    Filed: October 29, 2012
    Publication date: May 1, 2014
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yen-Ting Kuo, Ping-Cheng Hu, Yu-Fang Tsai
  • Patent number: 8704341
    Abstract: Semiconductor packages and related methods. The semiconductor package includes a substrate, a semiconductor chip, a package body, a recess and a conductive layer. The substrate includes a grounding element. The semiconductor chip is disposed on the substrate and has a lateral surface and an upper surface. The package body encapsulates the lateral surface of the semiconductor chip. The recess is formed in the package body and exposes the upper surface of the semiconductor chip. The conductive layer covers an outer surface of the package body, the grounding element and the upper surface of the semiconductor chip exposed by the recess to provide both thermal dissipation and EMI shielding for the semiconductor chip.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: April 22, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: I-Chia Lin, Yu-Chou Tseng, Jin-Feng Yang, Chi-Sheng Chung, Kuo-Hsien Liao
  • Patent number: 8698307
    Abstract: A semiconductor package includes a substrate and a semiconductor device. The semiconductor device includes a body having a center, a layer disposed adjacent to the body, and a plurality of conductive pillars configured to electrically connect the semiconductor device to the substrate. The layer defines a plurality of openings. Each of the plurality of conductive pillars extends at least partially through a corresponding one of the plurality of openings. An offset between a first central axis of the each of the plurality of conductive pillars and a second central axis of the corresponding one of the plurality of openings varies with distance between the first central axis and the center of the body. The second central axis of the corresponding one of the plurality of openings is disposed between the first central axis of the each of the plurality of conductive pillars and the center of the body.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: April 15, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Meng-Kai Shih, Chang-Chi Lee
  • Patent number: 8692362
    Abstract: A semiconductor structure includes a plurality of thermal vias and a heat dissipation layer disposed at a periphery of a back surface of a lower chip in a stacked-chip package. This arrangement improves solderability of a subsequently-bonded heat sink. Additionally, the thermal vias and the heat dissipation layer provide an improved thermal conduction path for enhancing heat dissipation efficiency of the semiconductor structure. A method for manufacturing the semiconductor structure is also provided.
    Type: Grant
    Filed: May 7, 2011
    Date of Patent: April 8, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Meng-Jen Wang
  • Patent number: 8691625
    Abstract: The present invention relates to a method for making a chip package. The method includes the following steps: (a) providing a substrate having at least one conductive via; (b) disposing the substrate on a carrier; (c) removing part of the substrate, so as to expose the conductive via, and form at least one through via; (d) disposing a plurality of chips on a surface of the substrate, wherein the chips are electrically connected to the through via of the substrate; (e) forming an encapsulation; (f) removing the carrier; (g) conducting a flip-chip mounting process; (h) removing the encapsulation; and (i) forming a protective material. Whereby, the carrier and the encapsulation can avoid warpage of the substrate during the manufacturing process.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: April 8, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Meng-Jen Wang
  • Patent number: 8686568
    Abstract: The package substrate includes a core, a plurality of first circuit segments, and a plurality of conductive pillars. Each of the first circuit segments has a patterned metal layer disposed on the core, a barrier layer disposed on the patterned metal layer, and an upper metal pattern disposed on the barrier layer. The conductive pillars penetrate the core, the patterned metal layer, and the barrier layer, and contact the upper metal pattern. The conductive pillars are formed from a material that can be selectively removed without affecting the barrier layer.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: April 1, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Sheng-Ming Wang, Hsiang-Ming Feng, Yen-Hua Kuo
  • Patent number: 8685863
    Abstract: The present invention relates to a semiconductor process, a semiconductor element and a package having a semiconductor element. The semiconductor element includes a base material and at least one through via structure. The base material has a first surface, a second surface, at least one groove and at least one foundation. The groove opens at the first surface, and the foundation is disposed on the first surface. The through via structure is disposed in the groove of the base material, and protrudes from the first surface of the base material. The foundation surrounds the through via structure. Whereby, the foundation increases the strength of the through via structure, and prevents the through via structure from cracking.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: April 1, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Bin-Hong Cheng
  • Publication number: 20140087519
    Abstract: A package process is provided. An adhesive layer is disposed on a carrier board and then plural first semiconductor devices are disposed on the adhesive layer. A first molding compound formed on the carrier board covers the sidewalls of the first semiconductor devices and fills the gaps between the first semiconductor devices so as to form a chip array board constructed by the first semiconductor devices and the first molding compound. Next, plural second semiconductor devices are flip-chip bonded to the first semiconductor devices respectively. Then, a second molding compound formed on the chip array board at least covers the sidewalls of the second semiconductor devices and fills the gaps between the second semiconductor devices. Subsequently, the chip array board is separated from the adhesive layer. Then, the first and the second molding compound are cut along the gaps between the second semiconductor devices.
    Type: Application
    Filed: November 22, 2013
    Publication date: March 27, 2014
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chi-Chih Shen, Jen-Chuan Chen, Tommy Pan
  • Publication number: 20140084480
    Abstract: The package substrate includes a core, a plurality of first circuit segments, and a plurality of conductive pillars. Each of the first circuit segments has a patterned metal layer disposed on the core, a barrier layer disposed on the patterned metal layer, and an upper metal pattern disposed on the barrier layer. The conductive pillars penetrate the core, the patterned metal layer, and the barrier layer, and contact the upper metal pattern. The conductive pillars are formed from a material that can be selectively removed without affecting the barrier layer.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Sheng-Ming Wang, Hsiang-Ming Feng, Yen-Hua Kuo
  • Publication number: 20140084475
    Abstract: The substrate includes a first dielectric layer, a first circuit pattern, a plurality of pillars and a second circuit pattern. The first dielectric layer has opposing first and second dielectric surfaces. The first circuit pattern is embedded in the first dielectric layer and defines a plurality of curved trace surfaces. Each of the pillars has an exterior surface adapted for making external electrical connection and a curved base surface abutting a corresponding one of the trace surfaces. The second circuit pattern is on the second dielectric surface of the first dielectric layer and electrically connected to the first circuit pattern.
    Type: Application
    Filed: September 21, 2012
    Publication date: March 27, 2014
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tien-Szu Chen, Kuang-Hsiung Chen, Sheng-Ming Wang, Hsiang-Ming Feng, Yen-Hua Kuo
  • Patent number: 8674487
    Abstract: A semiconductor package with a die pad, a die disposed on the die pad, and a first lead disposed about the die pad. The first lead includes a contact element, an extension element extending substantially in the direction of the die pad, and a concave surface disposed between the contact element and the extension element. A second lead having a concave surface is also disposed about the die pad. The first lead concave surface is opposite in direction to the second lead concave surface.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: March 18, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Lin-Wang Yu, Ping-Cheng Hu, Che-Chin Chang, Yu-Fang Tsai
  • Patent number: 8673774
    Abstract: The present invention relates to a method for forming a via in a substrate. The method includes the following steps: (a) providing a substrate; (b) forming a groove that has a side wall and a bottom wall on a first surface of the substrate; (c) forming a first conductive metal on the side wall and the bottom wall of the groove so as to form a central groove; (d) forming a center insulating material in the central groove; (e) forming an annular groove that surrounds the first conductive metal on the first surface of the substrate; (f) forming a first insulating material in the annular groove; and (g) removing part of the substrate to expose the first conductive metal, the center insulating material and the first insulating material.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: March 18, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Meng-Jen Wang
  • Patent number: 8671562
    Abstract: A method for manufacturing a circuit board includes the steps of: forming a first wiring layer on a substrate; forming an insulating layer on the surface of the first wiring layer by means of electrophoretic deposition; forming a second wiring layer on the insulating layer and the surface of the substrate; and performing the follow-up procedures, such as forming a solder mask; thereby reducing the thickness of the circuit board and increasing the density of the circuit layout.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: March 18, 2014
    Assignee: Advanced Semiconductor Engineering Inc.
    Inventor: Chien Hao Wang
  • Patent number: 8665605
    Abstract: A substrate structure and a package structure using the same are provided. The substrate structure includes a number of traces, a substrate core and a number of first metal tiles. The substrate core has a first surface and a second surface opposite to the first surface. The first metal tiles are disposed on one of the first surface and the second surface, the minimum pitch between adjacent two of the first metal tiles is the minimum process pitch.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: March 4, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuo-Hua Chen, Ming-Chiang Lee, Tsung-Hsun Lee, Chen-Chuan Fan
  • Patent number: 8653633
    Abstract: Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit including a grounding element; (2) a semiconductor device disposed adjacent to an upper surface of the substrate unit; (3) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device; and (4) an EMI shield disposed adjacent to exterior surfaces of the package body and electrically connected to a connection surface of the grounding element. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit, and the connection surface of the grounding element is electrically exposed adjacent to the lateral surface of the substrate unit. The grounding element corresponds to a remnant of an internal grounding via, and provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield.
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: February 18, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuo-Hsien Liao, Chi-Tsung Chiu, Chih-Pin Hung
  • Patent number: 8653634
    Abstract: A wafer level package including a shield connected to a plurality of conductive elements disposed on a silicon wafer. The conductive elements are arranged to individually enclose micro-structure elements located on the silicon wafer within cavities formed by the conductive elements for better shielding performance. The shield and the conductive elements function as the EMI shield.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: February 18, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chi Tsung Chiu, Ying-Te Ou
  • Patent number: 8643167
    Abstract: The present invention relates to a stacked semiconductor package and a method for making the same. The method includes the steps of mounting a plurality of first dice to a wafer by conducting a reflow process; and thinning the wafer from the backside surface of the wafer, thereby reducing manufacturing time and preventing warpage.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: February 4, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chia-Lin Hung, Jen-Chuan Chen, Hui-Shan Chang, Kuo-Pin Yang
  • Patent number: 8637887
    Abstract: A chip package having a lead frame and a molded portion. The lead frame includes a thermal pad and at least one electrode. The molded portion partially encapsulates the at least one electrode such that it is exposed on a top surface but not on a bottom surface. A bottom surface of the thermal pad is exposed for direct securement to an external heat sink. The molded portion is disposed between the at least one electrode and the heat sink to prevent a short circuit.
    Type: Grant
    Filed: May 8, 2012
    Date of Patent: January 28, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Hsun-Wei Chan