Patents Assigned to Advanced Semiconductor Engineering
  • Patent number: 9024445
    Abstract: The present invention relates to a package having a semiconductor device. The semiconductor device includes a substrate body, a plurality of conductive vias and a plurality of metal pads. The conductive vias are disposed in the through holes of the substrate body. The metal pads are electrically connected to the conductive vias. At least one of the metal pads has at least one curved side wall and at least one reference side wall. The curvature of the curved side wall is different from that of the reference side wall, so as to allow the metal pads to be closer to each other. This arrangement allows the conductive to be closer to each other. Therefore, more conductive vias can be arranged in a limited space.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: May 5, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuo Hua Chen, Li Wen Tsai
  • Patent number: 9024689
    Abstract: A radio frequency (RF) power amplifier is disclosed. The RF power amplifier includes a bias circuit, an output stage circuit and dynamic bias controlling circuit. The bias circuit receives a system voltage and the bias circuit provides a working voltage according to the system voltage. The output stage circuit receives the working voltage so as to work at an operation bias point. The dynamic bias controlling circuit receives the working voltage and outputs a compensation voltage to the bias circuit according to a variation of the working voltage. When the input power increases and makes the working voltage decreases so as to shift the operation bias point, the bias circuit adjusts the working voltage upward so as to recover the operation bias point according to the compensation voltage received.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: May 5, 2015
    Assignee: Advanced Semiconductor Engineering Inc.
    Inventors: Jaw-Ming Ding, Chien-Yeh Liu
  • Patent number: 9013238
    Abstract: A radio frequency (RF) amplifier is disclosed. The RF power amplifier includes a bias circuit, an output-stage circuit and a RF compensation circuit. When a first system voltage is larger than a first voltage threshold value, the bias circuit generates a first current rising slightly. When first system voltage is larger than second voltage threshold value, the RF compensation circuit receives a second circuit rising slightly transmitted from the bias circuit. When the first system voltage is in an operation voltage range, the first current is larger than the second circuit so as to a quiescent operating current of the RF power amplifier is independent of change of the first system voltage. When the first system voltage is larger than a third voltage threshold value, the first current is equal to the second current so as to have the bias current being a zero current to protect the RF power amplifier from over-voltage.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: April 21, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Jaw-Ming Ding, Jia-Hong Mou, Hsin-Chin Chang
  • Patent number: 9007273
    Abstract: A semiconductor package integrated with conformal shield and antenna is provided. The semiconductor package includes a semiconductor element, an electromagnetic interference shielding element, a dielectric structure, an antenna element and an antenna signal feeding element. The electromagnetic interference shielding element includes an electromagnetic interference shielding film and a grounding element, wherein the electromagnetic interference shielding film covers the semiconductor element and the grounding element is electrically connected to the electromagnetic interference shielding layer and a grounding segment of the semiconductor element. The dielectric structure covers a part of the electromagnetic interference shielding element and has an upper surface. The antenna element is formed adjacent to the upper surface of the dielectric structure. The antenna signal feeding element passing through the dielectric structure electrically connects the antenna element and the semiconductor element.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: April 14, 2015
    Assignee: Advances Semiconductor Engineering, Inc.
    Inventors: Kuo-Hsien Liao, Chi-Hong Chan, Shih Fuyu
  • Patent number: 8994156
    Abstract: Electronic devices including a semiconductor device package, a substrate, and first and second solder joints. The semiconductor device package includes a die pad, leads and enhancement elements surrounding the die pad, a chip electrically connected to the leads, and a package body encapsulating the chip, portions of the leads, and portions of the enhancement elements, but leaving exposed at least a side surface of each enhancement element. Side surfaces of the enhancement elements and the package body are coplanar. The substrate includes first pads corresponding to the leads and second pads corresponding to the enhancement elements. The first solder joints are disposed between the first pads and the leads. The second solder joints are disposed between the second pads and the enhancement elements. The second solder joints contact side surfaces of the enhancement elements. The surface area of the second pads is greater than the surface area of the corresponding enhancement elements.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: March 31, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Po-Shing Chiang, Ping-Cheng Hu, Yu-Fang Tsai
  • Patent number: 8987734
    Abstract: The present invention provides a semiconductor wafer, semiconductor package and semiconductor process. The semiconductor wafer includes a substrate, at least one metal segment and a plurality of dielectric layers. The semiconductor wafer is defined as a plurality of die areas and a plurality of trench areas, each of the die areas has an integrated circuit including a plurality of patterned metal layers disposed between the dielectric layers. The trench areas are disposed between the die areas, and the at least one metal segment is disposed in the trench area and insulated from the integrated circuit of the die area.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 24, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Yung-Hui Wang
  • Patent number: 8975157
    Abstract: The present invention provides a temporary carrier bonding and detaching process. A first surface of a semiconductor wafer is mounted on a first carrier by a first adhesive, and a first isolation coating is disposed between the first adhesive and the first carrier. Then, a second carrier is mounted on the second surface of the semiconductor wafer. The first carrier is detached. The method of the present invention utilizes the second carrier to support and protect the semiconductor wafer, after which the first carrier is detached. Therefore, the semiconductor wafer will not be damaged or broken, thereby improving the yield rate of the semiconductor process. Furthermore, the simplicity of the detaching method for the first carrier allows for improvement in efficiency of the semiconductor process.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: March 10, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Wei-Min Hsiao
  • Patent number: 8963316
    Abstract: The present invention relates to a semiconductor device and a method for making the same. The semiconductor device includes a substrate, a first redistribution layer and a conductive via. The substrate has a substrate body and a pad. The pad and the first redistribution layer are disposed adjacent to the first surface of the substrate body, and electrically connected to each other. The interconnection metal is disposed in a through hole of the substrate body, and contacts the first redistribution layer. Whereby, the pad can be electrically connected to the second surface of the substrate body through the first redistribution layer and the conductive via.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: February 24, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chih-Jing Hsu, Ying-Te Ou, Chieh-Chen Fu, Che-Hau Huang
  • Patent number: 8963671
    Abstract: A semiconductor transformer includes a first coil inductor and a second coil inductor. The first coil inductor has a first port, a second port and a first coil inductor wall, the first coil inductor wall having a height substantially equal to a thickness of the substrate. The second coil inductor has a third port, a first extension wall connected to the third port, a fourth port, a second extension wall connected to the fourth port and a second coil inductor wall.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: February 24, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chi-Han Chen, Pao-Nan Lee, Chi Tsung Chiu, Chien Hua Chen
  • Patent number: 8957506
    Abstract: A quad flat non-leaded package including a leadframe, a chip, a plurality of first bonding wires and a molding compound is provided. The leadframe includes a plurality of first leads, and each first lead has a first portion and a second portion that extend along an axis. The length of the first portion is greater than the length of the second portion. The thickness of the first portion is greater than the thickness of the second portion. The chip is disposed on the leadframe and covers a portion of the first portions. The first bonding wires are connected between the chip and another portion of the first portions or the chip and the second portions, such that the chip is electrically connected to the first leads through the first bonding wires. The molding compound encapsulates a portion of the first leads, the chip and the first bonding wires.
    Type: Grant
    Filed: October 14, 2009
    Date of Patent: February 17, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yueh-Liang Hsu, Chi-Wen Chang
  • Patent number: 8952542
    Abstract: The present invention provides a semiconductor device, a semiconductor package and a semiconductor process. The semiconductor process includes the following steps: (a) providing a semiconductor wafer having a first surface, a second surface and a passivation layer; (b) applying a first laser on the passivation layer to remove a part of the passivation layer and expose a part of the semiconductor wafer; (c) applying a second laser, wherein the second laser passes through the exposed semiconductor wafer and focuses at an interior of the semiconductor wafer; and (d) applying a lateral force to the semiconductor wafer. Whereby, the cutting quality is ensured.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: February 10, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Pei Hsing Hua, Hui-Shan Chang
  • Patent number: 8941222
    Abstract: A semiconductor package includes at least one semiconductor die having an active surface, an interposer element having an upper surface and a lower surface, a package body, and a lower redistribution layer. The interposer element has at least one conductive via extending between the upper surface and the lower surface. The package body encapsulates portions of the semiconductor die and portions of the interposer element. The lower redistribution layer electrically connects the interposer element to the active surface of the semiconductor die.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: January 27, 2015
    Assignee: Advanced Semiconductor Engineering Inc.
    Inventor: John Richard Hunt
  • Patent number: 8937015
    Abstract: The present invention relates to a method for forming a via in a substrate which includes the flowing steps of: (a) providing a substrate having a first surface and a second surface; (b) forming an accommodating groove and a plurality of pillars on the first surface of the substrate, the accommodating groove having a side wall and a bottom wall, the pillars remaining on the bottom wall of the accommodating groove; (c) forming a first insulating material in the accommodating groove and between the pillars; (d) removing the pillars so as to form a plurality of grooves in the first insulating material; and (e) forming a first conductive metal in the grooves. As a result, thicker insulating material can be formed in the via, and the thickness of the insulating material in the via is even.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: January 20, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Meng-Jen Wang, Chung-Hsi Wu
  • Patent number: 8937376
    Abstract: Semiconductor packages including a die pad, at least one connecting bar, at least one supporting portion, a plurality of leads, a semiconductor chip, a heat sink and a molding compound. The connecting bar connects the die pad and the supporting portion. The leads are electrically isolated from each other and the die pad. The semiconductor chip is disposed on the die pad and electrically connected to the leads. The heat sink is supported by the supporting portion. The molding compound encapsulates the semiconductor chip and the heat sink. Heat from the semiconductor chip is efficiently dissipated from the die pad through the connecting bar, through the supporting portion, and through the heat sink.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: January 20, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Fu-Yung Tsai
  • Patent number: 8937387
    Abstract: The disclosure concerns a semiconductor device having conductive vias. In an embodiment, the semiconductor device includes a substrate having at least one conductive via formed therein. The conductive via has a first end substantially coplanar with an inactive surface of the substrate. A circuit layer is disposed adjacent to an active surface of the substrate and electrically connected to a second end of the conductive via. A redistribution layer is disposed adjacent to the inactive surface of the substrate, the redistribution layer having a first portion disposed on the first end an electrically connected thereto, and a second portion positioned upward and away from the first portion. A die is disposed adjacent to the inactive surface of the substrate and electrically connected to the second portion of the redistribution layer.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: January 20, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Che-Hau Huang, Ying-Te Ou
  • Patent number: 8922028
    Abstract: The present invention relates to a semiconductor package, comprising a carrier, a semiconductor device, a first wire and a second wire. The carrier has a first electrically connecting portion and a second electrically connecting portion. The semiconductor device has a plurality of pads. The first wire electrically connects one of the pads of the semiconductor device and the first electrically connecting portion of the carrier, and the first wire has a first length. The second wire electrically connects one of the pads of the semiconductor device and the second electrically connecting portion of the carrier, and the second wire has a second length. The second length is larger than the first length, and the diameter of the second wire is larger than that of the first wire. Thus, the material usage for the wire is reduced, and the manufacturing cost is reduced.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: December 30, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Sung-Ching Hung, Wen-Pin Huang
  • Publication number: 20140346654
    Abstract: A chip package comprising a carrier, a chip, a plurality of first conductive elements, an encapsulation, and a conductive film is provided. The carrier has a carrying surface and a back surface opposite to the carrying surface. Furthermore, the carrier has a plurality of common contacts in the periphery of the carrying surface. The chip is disposed on the carrying surface and electrically connected to the carrier. In addition, the first conductive elements are disposed on the common contacts respectively. The encapsulation is disposed on the carrying surface and encapsulating the chip. Moreover, the conductive film is disposed over the encapsulation and the first conductive elements, so as to electrically connect with the common contacts via the first conductive elements. A process for fabricating the chip package is further provided. The chip package is capable of preventing the EMI problem and thus provides superior electrical performance.
    Type: Application
    Filed: June 2, 2014
    Publication date: November 27, 2014
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Soo-Min CHOI, Hyeong-No KIM, Jae-Sun AN, Young-Gue LEE, Sang-Jin CHA
  • Patent number: 8889488
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a substrate, a semiconductor element, a package body and a conductive part. The substrate has an electrical contact. The semiconductor element is disposed on the substrate. The package body covers the semiconductor element and defines a through hole from which the electrical contact is exposed. Wherein, the package body includes a resin body and a plurality of fiber layers. The fiber layers are disposed in the resin body and define a plurality of fiber apertures which is arranged as an array. The conductive part is electrically connected to the substrate through the through hole.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: November 18, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Shin-Hua Chao, Chao-Yuan Liu, Hui-Ying Hsieh, Chih-Ming Chung
  • Publication number: 20140332957
    Abstract: The present disclosure relates to a semiconductor package and a manufacturing method thereof The semiconductor package includes a semiconductor element including a main body, a plurality of conductive vias, and at least one filler. The conductive vias penetrate through the main body. The filler is located in the main body, and a coefficient of thermal expansion (CTE) of the filler is different from that of the main body and the conductive vias. Thus, the CTE of the overall semiconductor element can be adjusted, so as to reduce warpage.
    Type: Application
    Filed: May 9, 2014
    Publication date: November 13, 2014
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chin-Li KAO, Chang-Chi LEE, Yi-Shao LAI
  • Patent number: 8884424
    Abstract: A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: November 11, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yuan-Chang Su, Shih-Fu Huang, Chia-Cheng Chen, Tzu-Hui Chen, Kuang-Hsiung Chen, Pao-Ming Hsieh, Ming Chiang Lee, Bernd Karl Appelt