Abstract: A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.

Abstract: The present invention relates to a semiconductor package and a semiconductor device and a method of making the same. The method of making the semiconductor package comprises: providing a substrate; attaching a chip to a surface of the substrate; forming a plurality of connecting elements for electrically connecting the chip and the substrate; forming a plurality of first conductive bodies on the surface of the substrate; forming a molding compound for encapsulating the surface of the substrate, the chip, the connecting elements and the first conductive bodies; and removing a part of a border portion of the molding compound, so that the molding compound has two heights and one end of each first conductive bodies is exposed. Thereby, the molding compound covers the entire surface of the substrate, so that the bonding pads on the surface of the substrate will not be polluted.

Abstract: The present invention provides a temporary carrier bonding and detaching process. A first surface of a semiconductor wafer is mounted on a first carrier by a first adhesive layer, and a first isolation coating disposed between the first adhesive layer and the first carrier. Then, a second carrier is mounted on the second surface of the semiconductor wafer. The first carrier is detached. Then, the first surface of the semiconductor wafer is mounted on a film frame. The second carrier is detached. The method of the present invention utilizes the second carrier to support and protect the semiconductor wafer, after which the first carrier is detached. Therefore, the semiconductor wafer will not be damaged or broken, thereby improving the yield rate of the semiconductor process. Furthermore, the simplicity of the detaching method for the first carrier allows for improvement in efficiency of the semiconductor process.

Abstract: The substrate includes a first dielectric layer, a first circuit pattern, a plurality of pillars and a second circuit pattern. The first dielectric layer has opposing first and second dielectric surfaces. The first circuit pattern is embedded in the first dielectric layer and defines a plurality of curved trace surfaces. Each of the pillars has an exterior surface adapted for making external electrical connection and a curved base surface abutting a corresponding one of the trace surfaces. The second circuit pattern is on the second dielectric surface of the first dielectric layer and electrically connected to the first circuit pattern.

Abstract: A chip package comprising a carrier, a chip, a plurality of first conductive elements, an encapsulation, and a conductive film is provided. The carrier has a carrying surface and a back surface opposite to the carrying surface. Furthermore, the carrier has a plurality of common contacts in the periphery of the carrying surface. The chip is disposed on the carrying surface and electrically connected to the carrier. In addition, the first conductive elements are disposed on the common contacts respectively. The encapsulation is disposed on the carrying surface and encapsulating the chip. Moreover, the conductive film is disposed over the encapsulation and the first conductive elements, so as to electrically connect with the common contacts via the first conductive elements. A process for fabricating the chip package is further provided. The chip package is capable of preventing the EMI problem and thus provides superior electrical performance.

Abstract: The present invention relates to a semiconductor structure having an integrated passive network and a method for making the same. The semiconductor structure includes a substrate which can be an interposer. The substrate can include a plurality of conductive vias. In various embodiments, the substrate includes a dielectric layer disposed thereon, the dielectric layer having an opening forming a straight hole allowing electrical connection between the passive network and the conductive via. The passive network includes a series of patterned dielectric and conductive layers, forming passive electronic components. In an embodiment, the passive device includes a common resistor coupled to a pair of inductors, each of the inductors coupled to a capacitor. In another embodiment, the passive device includes a resistor and an inductor electrically connected to each other, a bottom surface of the inductor coplanar with a bottom surface of the resistor.

Abstract: The present invention provides a semiconductor wafer, a semiconductor chip and a semiconductor package. The semiconductor wafer includes a first pad, a first inter-layer dielectric and a second pad. The first pad is disposed on a top surface of a semiconductor substrate and has a solid portion and a plurality of through holes. The first inter-layer dielectric covers the first pad. The second pad is disposed on the first inter-layer dielectric and has a solid portion and a plurality of through holes, wherein the through holes of the first pad correspond to the solid portion of the second pad.

Abstract: A light emitting package includes a metal plate, a plurality of LED chips, a plurality of leads and a molding compound. The metal plate has a first surface and a second surface, and is bent into two chip mounting portions, wherein an inclination angle is between the chip mounting portions. The LED chips are mounted on the first surface and the second surface of the chip mounting portions. The leads are disposed adjacent to the metal plate and electrically connected to the LED chips. The molding compound encapsulates the LED chips and a part of the lead.

Abstract: A semiconductor device package with an interposer, which serves as an intermediate or bridge circuit of various electrical pathways in the package to electrically connect any two or more electrical contacts, such as any two or more electrical contacts of a substrate and a chip. In particular, the interposer provides electrical pathways for simplifying a circuit layout of the substrate, reducing the number of layers of the substrate, thereby reducing package height and manufacturing cost. Furthermore, the tolerance of the circuit layout can be increased or maintained, while controlling signal interference between adjacent traces and accommodating high density circuit designs. Moreover, the package is suitable for a PoP process, where a profile of top solder balls on the substrate and a package body can be varied according to particular applications, so as to expose at least a portion of each of the top solder balls and electrically connect the package to another device through the exposed, top solder balls.

Abstract: The semiconductor package includes a substrate, a die, a first metal layer, a second metal layer and an optional seed layer. The package body at least partially encapsulates the die on the substrate. The seed layer is disposed on the package body and the first metal layer is disposed on the seed layer. The second metal layer is disposed on the first metal layer and the lateral surface of the substrate. The first metal layer and the second metal layer form an outer metal cap that provides thermal dissipation and electromagnetic interference (EMI) shielding.

Abstract: A heatsink and a heatsink-positioning system. The heatsink-positioning system includes a heatsink and a positioning device. The heatsink includes a circular top, a ring-shaped sidewall and a plurality of foot portions. The ring-shaped sidewall connects to the circular top and extends away from the circular top. The ring-shaped sidewall has at least one first positioning portion used for fixing the heatsink. The foot portions connect to the ring-shaped sidewall and extend away from the ring-shaped sidewall. Each foot portion has an opening. The positioning device has at least one second positioning portion corresponding to the first positioning portion and is used for fixing the first positioning portion. By utilizing the heatsink-positioning system, the problem of displacement of the heatsink can be improved.

Abstract: A semiconductor package includes a substrate, a semiconductor die, a package body, an electromagnetic interference shield, a dielectric structure and an antenna element. The substrate comprises a grounding segment and a feeding point. The semiconductor die is disposed on the substrate. The package body encapsulates the semiconductor die. The electromagnetic interference shield is formed on the package body. The dielectric structure encapsulates the electromagnetic interference shield. The antenna element is formed on the dielectric structure and electrically connecting the grounding segment of the substrate and the feeding point.

Abstract: A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts a connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier.

Abstract: The present invention relates to a semiconductor element having conductive vias and a semiconductor package having a semiconductor element with conductive vias and a method for making the same. The semiconductor element having conductive vias includes a silicon substrate and at least one conductive via. The thickness of the silicon substrate is substantially in a range from 75 to 150 ?m. The conductive via includes a first insulation layer and a conductive metal, and the thickness of the first insulation layer is substantially in a range from 5 to 19 ?m. Using the semiconductor element and the semiconductor package of the present invention, the electrical connection between the conductive via and the other element can be ensured, and the electrical connection between the silicon substrate and the other semiconductor element can be ensured, so as to raise the yield rate of a product.

Abstract: A stacked package device includes a substrate, at least one electronic component and a molding unit. The molding unit includes a first insulation layer, a second insulation layer, and a first shielding layer. The electronic component is disposed on the substrate. The first insulation layer is disposed on the substrate and covers the electronic component. The first insulation layer has a plurality of holes, and is disposed on the first insulation layer. The second insulation layer is disposed on the first shielding layer. The first insulation layer is connected to the second insulation layer through the holes.

Abstract: An embodiment of a method for making semiconductor device packages includes a heat sink matrix and a substrate. A plurality of semiconductor devices are attached to the substrate. Then, a package body is formed between the heat sink matrix and the substrate, wherein the package body encapsulates the semiconductor devices. Then, a plurality of first cutting slots is formed, wherein the first cutting slots extend through the heat sink matrix and partially extend into the package body. Then, a plurality of second cutting slots is formed, wherein the second cutting slots extend through the substrate and through the package body to the first cutting slot, thereby singulating the heat sink matrix and substrate into a plurality of individual semiconductor device packages.

Abstract: The present invention relates to a semiconductor structure and a method for making the same. The method includes the following steps: (a) providing a first wafer and a second wafer; (b) disposing the first wafer on the second wafer; (c) removing part of the first wafer, so as to form a groove; (d) forming a through via in the groove; and (e) forming at least one electrical connecting element on the first wafer. Therefore, the wafers are penetrated and electrically connected by forming only one conductive via, which leads to a simplified process and a low manufacturing cost.

Abstract: The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, a first capacitor, a first protective layer, a first metal layer and a second protective layer. The substrate has at least one via structure. The first capacitor is disposed on a first surface of the substrate. The first protective layer encapsulates the first capacitor. The first metal layer is disposed on the first protective layer, and includes a first inductor. The second protective layer encapsulates the first inductor. Whereby, the first inductor, the first capacitor and the via structure are integrated into the semiconductor package, so that the size of the product is reduced.

Abstract: A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; (c) a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts are connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier.

Abstract: A substrate structure is provided. The substrate structure includes a number of traces, a substrate core, a number of first metal tiles, a number of second metal tiles, a number of first electrically-functioning circuits, and a number of second electrically-functioning circuits. The substrate core has a first surface and a second surface opposite to the first surface. The traces, the first metal tiles, and the first electrically-functioning circuits are disposed on the first surface and add up to a first metal structure proportion, and the second metal tiles and the second electrically-functioning circuits are disposed on the second surface and add up to a second metal structure proportion. The difference between the first metal structure proportion and the second metal structure proportion is within 15%.