Abstract: A semiconductor module includes two or more semiconductor dies and an interconnect structure coupled to the two or more semiconductor dies. The interconnect structure implements a plurality of die-to-die connection pathways having a first density and a plurality of fan-out redistribution pathways having a second density that is different from the first density.

Abstract: A method for emulating a reactive source impedance for a generator connected to a load. The method comprises adjusting an output of the generator, wherein, in response to adjustment of the output, a first measured value M1 calculated with respect to a weighted sum of voltage v, current i and derivatives of the voltage v and the current i tends to a first setpoint S1 for M1. The method also includes receiving a second setpoint S2 for a second measured value M2 and adjusting S1 to adjust the second measured value M2 of a conventional measure of generator output towards the second setpoint S2 for M2, wherein holding M1 constant emulates a desired source impedance of the generator.

Abstract: The present invention relates to a method of preparing a shape-reconfigurable micropatterned polymer haptic material using an electric field technique, and more particularly, to a method of preparing a shape-reconfigurable micro-patterned polymer thin film and a haptic material by controlling the orientation of a liquid-crystalline organic polymer using an electric field control system and inducing the generation of defect structures having a regular microstructure array in a polymer film.

Abstract: A data processor that is operable to be coupled to a memory includes a memory operation array, a controller, a refresh logic circuit, and a selector. The memory operation array is for storing memory operations for a first power state of the memory. The controller is responsive to a power state change request to execute a plurality of memory operations from the memory operation array when the first power state is selected. The refresh logic circuit generates refresh cycles periodically for the memory. The selector is for multiplexing the refresh cycles with the memory operations during a power state change to the first power state.

Abstract: An accelerated processing device is provided which comprises a plurality of compute units each including a plurality of SIMD units, and each SIMD unit comprises a register file. The accelerated processing device also comprises LDS in communication with each of the SIMD units. The accelerated processing device also comprises a first portion of cache memory, in communication with each of the SIMD units and a second cache portion of memory shared by the compute units. The compute units are configured to execute a program in which a storage portion of at least one of the register file of a SIMD unit, the first portion of cache memory and the LDS is reserved as part of another of the register file, the first portion of cache memory and the LDS.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a carrier having a first side and a second side adjacent to the first side. The semiconductor device also includes a first antenna adjacent to the first side and configured to operate at a first frequency and a second antenna adjacent to the second side and configured to operate at a second frequency different from the first frequency. An method of manufacturing a semiconductor device is also provided.

Abstract: A method and apparatus for integrating data compression in a computer system includes receiving first data at a first system level. Based upon a number of planes of the first data being less than or equal to a threshold, the data is compressed with a first data compression scheme, and transferred to a second system level for processing. Based upon the number of planes of the first data exceeding the threshold, the first data is transferred uncompressed to the second system level for processing. Based upon the received data at the second system level being compressed with the first compression scheme, the data is transferred to a third system level, and based upon the received data at the second system level being uncompressed with the first compression scheme, compressing the data with a second compression scheme, and transferring the compressed data to the third system level.

Abstract: Disclosed are a 3D non-volatile memory, an operating method thereof, and a manufacturing method thereof. The 3D non-volatile memory includes a bit line formed to extend in a vertical direction and horizontal structures contacting the bit line while being formed to extend in a horizontal direction and being space in the vertical direction. Each of the horizontal structures includes a ferroelectric layer contacting the bit line, a middle metal layer surrounded by the ferroelectric layer, a dielectric layer surrounded by the middle metal layer, and a word line surrounded by the dielectric layer.

Abstract: A package structure includes: 1) a circuit substrate; 2) a first semiconductor device disposed on the circuit substrate; 3) a first insulation layer covering a sidewall of the first semiconductor device; 4) a second insulation layer covering the first insulation layer; and 5) a third insulation layer disposed on the circuit substrate and in contact with the second insulation layer.

Abstract: A composite coating layer for a solid oxide fuel cell member according to the present disclosure includes a nickel layer that coats at least a portion of the surface of the solid oxide fuel cell member, and a lanthanum oxide layer that coats at least a portion of the surface of the nickel layer, and thereby, has an effect of suppressing the volatilization of chromium from the solid oxide fuel cell member even under high temperature and long-term conditions.

Abstract: A semiconductor package device and a method of manufacturing a semiconductor package device are provided. The semiconductor package device includes a substrate, a first electronic component, a first dielectric layer, and a first hole. The substrate has a first surface and a second surface opposite to the first surface. The first electronic component is disposed on the first surface. The first dielectric layer is disposed on the second surface and has a third surface away from the substrate. The first hole extends from the first dielectric layer and the substrate. The first hole is substantially aligned with the first electronic component.

Abstract: The disclosure provides for an apparatus for intraocular lens selection. The apparatus may include a biometer and an autorefractor. The biometer may be configured to obtain at least two ocular measurement parameters for an eye. The autorefractor may be configured to obtain a post-operative refraction of the eye. The apparatus may also include a user interface configured to obtain a lens selection parameter for the eye, a memory, and a processor communicatively coupled to the biometer, the user interface, the autorefractor, and the memory. The processor may be configured to determine an intraocular lens power based on a formula using the at least two ocular measurement parameters. The processor may be configured to correlate the at least two ocular measurement parameters, the intraocular lens power, and the post-operative refraction as a training set.

Abstract: An apparatus and method for efficiently supporting multiple peripheral communication protocols in a computing system. A computing system includes multiple servers with one or more of the servers using multiple connectors for connecting to multiple peripheral devices such as data storage devices. At least one of the connectors is able to support multiple communication protocols, rather than a single communication protocol. A processor of the server determines a peripheral device has been attached to a connector that supports multiple communication protocols, and the processor determines whether one of the multiple communication protocols supported by the particular connector matches the attached peripheral device's communication protocol. If so, the processor configures the connector with the matching communication protocol. Otherwise, the processor generates an indication that specifies that there is no match.

Abstract: A corrugated pipe manufacturing cell is configured to produce multiple corrugated pipes in parallel. The manufacturing cell may comprise an extrusion system that is capable of providing multiple independently regulated flows of plastic piping material to multiple die heads. The multiple die heads may feed a set of mold blocks having dual cavities for forming he multiple corrugated pipes. The pipe manufacturing cell may be converted between a first mode for producing large diameter single corrugated pipes, and a second mode for producing smaller diameter, plural corrugated pipes.

Abstract: A package structure is provided. The package structure includes a substrate, a sensing device, a light transmissive member, and a bonding structure. The sensing device is over the substrate, and the light transmissive member is over the sensing device. The bonding structure has an upper surface connected to the light transmissive member and a lower surface connected to the sensing device. A width of the upper surface is less than a width of the lower surface of the bonding structure.

Abstract: A sleeve adapter for installation over a corrugated pipe is provided. The sleeve adapter may comprise a tubular body, wherein the tubular body may have a smooth outer surface, a first monofilament wire connected by a first one-way clamp, wherein the first monofilament wire may extend around a first end of the tubular body, a second monofilament wire connected by a second one-way clamp, wherein the second monofilament wire may extend around a second end of the tubular body, a flexible elastomer hinge extending around the tubular body, and a plurality of sealing surface fins extending outwardly from an inner surface of the tubular body.

Abstract: A circuit design emulation system having a plurality of integrated circuits (ICs) includes a first IC. The first IC includes an originator circuit configured to issue a request of a transaction directed to a completer circuit. The request is specified in a communication protocol. The first IC includes a completer transactor circuit coupled to the originator circuit and configured to translate the request into request data. The first IC includes a first interface circuit configured to synchronize the request data from an originator clock domain to a transceiver clock domain operating at a higher frequency than the originator clock domain. The first IC includes a first transceiver circuit configured to convey the request data over a communication link that operates asynchronously to the originator clock domain.

Abstract: A semiconductor device package includes a number of interposers mounted to the carrier, wherein the number of interposers may be arranged in an irregular pattern.

Abstract: A DRAM is configured using a triple-mode memory cell that supports a computation mode, a memory mode, and a data conversion mode by one cell and converts modes as necessary, and an AI accelerator using the same is provided, so that a dataflow may be reconfigured according to a structure and a size of an AI neural network (so-called deep neural network) to be trained.

Abstract: A bundle of carbon nanotubes (CNT), comprising a plurality of CNT with lengths of at least about 7 microns, wherein the bundle has a diameter of less than about 12 nm.