Patents Assigned to ADVANCED
  • Patent number: 12259084
    Abstract: This disclosure relates generally to corrugated pipe, and more particularly to corrugated pipe with an outer wrap. In one embodiment, a pipe includes an axially extended bore defined by a corrugated outer wall having axially adjacent, outwardly-extending corrugation crests, separated by corrugation valleys. The pipe also includes an outer wrap applied to the outer wall. The outer wrap may include fibers and plastic. The outer wrap may span the corrugation crests producing a smooth outer surface.
    Type: Grant
    Filed: January 23, 2024
    Date of Patent: March 25, 2025
    Assignee: Advanced Drainage Systems, Inc.
    Inventors: Bill Russell Vanhoose, Nicholas James Piazza, Ronald Robert Vitarelli, Owen Michael Atchison, Tyler James Frost
  • Patent number: 12260120
    Abstract: An electronic device includes a processor that executes a guest operating system; a memory having a guest portion that is reserved for storing data and information to be accessed by the guest operating system; and an input-output memory management unit (IOMMU). The IOMMU writes, in the guest portion, information into guest buffers and/or logs used for communicating information from the IOMMU to the guest operating system. The IOMMU also reads, from the guest portion, information in guest buffers and/or logs used for communicating information from the guest operating system to the IOMMU.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: March 25, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Maggie Chan, Philip Ng, Paul Blinzer
  • Patent number: 12260225
    Abstract: A system for providing system level sleep state power savings includes a plurality of memory channels and corresponding plurality of memories coupled to respective memory channels. The system includes one or more processors operative to receive information indicating that a system level sleep state is to be entered and in response to receiving the system level sleep indication, moves data stored in at least a first of the plurality of memories to at least a second of the plurality of memories. In some implementations, in response to moving the data to the second memory, the processor causes power management logic to shut off power to: at least the first memory, to a corresponding first physical layer device operatively coupled to the first memory and to a first memory controller operatively coupled to the first memory and place the second memory in a self-refresh mode of operation.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: March 25, 2025
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Jyoti Raheja, Hideki Kanayama, Guhan Krishnan, Ruihua Peng
  • Patent number: 12257157
    Abstract: A process for printing a talus implant comprising the steps of scanning a joint for a damaged talus, and scanning a contralateral joint for a healthy talus. Next, the process includes obtaining dimensions for a talus based upon an initial scan and then obtaining dimensions for a talus based upon the scan of the contralateral joint. Next the process includes inverting the dimensions of the talus in the contralateral joint and then comparing the dimensions of the calculated talus with a pre-set of dimensions in a database. Next the process includes exporting a set of dimensions to a printer to print a talus implant.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: March 25, 2025
    Assignee: Paragon Advanced Technologies, Inc.
    Inventors: Gregory J. Kowalczyk, Selene G. Parekh, Luciano Bernardino Bertolotti
  • Patent number: 12261089
    Abstract: A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.
    Type: Grant
    Filed: January 2, 2024
    Date of Patent: March 25, 2025
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tsung-Yu Lin, Pei-Yu Wang, Chung-Wei Hsu
  • Patent number: 12257458
    Abstract: The present application provides an ultrasonic wake-up system. The system includes an ultrasonic imaging device, an ultrasound stimulation device, and an ultrasound stimulation effect evaluation device, and acquires an ultrasonic image of a target object through the ultrasonic imaging device, transmits an ultrasound to the target object based on the ultrasonic image through the ultrasound stimulation device, and adjusts the transmitted ultrasound required through the ultrasound stimulation effect evaluation device. Therefore, peripheral nerves are accurately stimulated, an uplink reticular wake-up system is activated, so as to wake up patients with disorders of consciousness.
    Type: Grant
    Filed: May 30, 2023
    Date of Patent: March 25, 2025
    Assignee: SHENZHEN INSTITUTES OF ADVANCED TECHNOLOGY CHINESE ACADEMY OF SCIENCES
    Inventors: Hairong Zheng, Wei Zhou, Long Meng, Lili Niu, Zhengrong Lin, Xiaowei Huang, Junjie Zou
  • Patent number: 12262570
    Abstract: Provided are an organic electric element, a display panel and a display device having high efficiency or long life by including layers having excellent hole transport ability and carrier resistance.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: March 25, 2025
    Assignees: LG DISPLAY CO., LTD., SOLUS ADVANCED MATERIALS CO., LTD.
    Inventors: Seonkeun Yoo, Heejun Park, Soyoung Jang, Jiho Baek, Jeongdae Seo, Sunkap Kwon, Minchul Jun, Hyunchul Choi, Young Mo Kim, Jae Yi Sim
  • Patent number: 12258656
    Abstract: The present invention relates to a magnesium alloy material, which is an in situ magnesium hydroxide nanosheet layer modified magnesium alloy. The material is prepared from a magnesium alloy through a hydrothermal reaction under alkaline condition. The protective effect of the in situ formed magnesium hydroxide nanosheet layer structure results in remarkably enhanced corrosion resistance of the magnesium alloy, meanwhile the biocompatibility can also be significantly improved since the release rate of magnesium ion can be significantly reduced. In addition, the two-dimensional nanolayer structure has a non-releasing physical antibacterial property depending on contact. Therefore, the magnesium alloy material according to the present invention has an extremely great application prospect in the field of medical implant.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: March 25, 2025
    Assignee: SHENZHEN INSTITUTES OF ADVANCED TECHNOLOGY CHINESE ACADEMY OF SCIENCES
    Inventors: Guomin Wang, Huaiyu Wang, Kimho Paul Chu
  • Patent number: 12259110
    Abstract: The present disclosure provides an optical packaging structure and a backlight module with the optical packaging structure. The optical packaging structure includes a light-emitting chip, a packaging layer, a fluorescent layer, a lens structure, and a reflecting layer. The light-emitting chip includes a light-emitting surface, a connecting surface, and a side surface. The packaging layer covers the light-emitting surface and the first side surface. The connecting surface is exposed from the packaging layer. The fluorescent layer is disposed on the packaging layer, and covers on the light-emitting surface and the first side surface. The lens structure is disposed on a top surface of the fluorescent layer. A surface of the lens structure is recessed towards the light-emitting chip to form a curved surface. The reflecting layer is disposed on the curved surface.
    Type: Grant
    Filed: August 19, 2024
    Date of Patent: March 25, 2025
    Assignee: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.
    Inventors: Chuang-Yu Hsieh, Hsin-Ting Hung, Hao-Hsiang Hsieh, Shih-Hsiang Lo
  • Patent number: 12259958
    Abstract: Connected computing enables the use of highly diverse environments that support operating frameworks for contemporary civilization. But computing productivity and trustworthiness are undermined by such environments' largely inchoate organization. These environments and their identity infrastructures are fragmented, and unnecessarily unreliable, insecure, and insufficiently informative due to current computing entity (e.g., resource) identification infrastructure design, which lacks root identification reliability. Such reliability is enabled herein by a fundamentally accurate and authenticity ensuring, near-existential or existential quality, biometrically and liveness based, portable identification and provenance infrastructure. Such an infrastructure provides ubiquitously available identification information that can be used universally for identification processes.
    Type: Grant
    Filed: November 30, 2023
    Date of Patent: March 25, 2025
    Assignee: Advanced Elemental Technologies, Inc.
    Inventors: Victor Henry Shear, Timothy St. John Redmond, Jaisook Rho, Jason Ben Shear, Bruce Jason Tromberg, Robert George Wong
  • Patent number: 12258164
    Abstract: A method for preparing a package that can effectively suppress surface alteration even in a sputtering target whose surface is likely to be altered by moisture such as a sputtering target comprising an oxide of boron is provided. A method for preparing a package of sputtering target, including a step 1 of housing a sputtering target in a first packaging bag made of a film having a water vapor permeability of 1 g/(m2·24 h) or less, and then vacuum sealing an opening of the first packaging bag; and a step 2 of housing the first packaging bag which has been vacuum sealed in the step 1, in a second packaging bag made of a film having a water vapor permeability of 1 g/(m2·24 h) or less, and then enclosing one or more cushion gases selected from a group consisting of air and inert gas in the second packaging bag, and sealing an opening of the second packaging bag.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: March 25, 2025
    Assignee: JX Advanced Metals Corporation
    Inventor: Shin-ichi Ogino
  • Patent number: 12259767
    Abstract: Performance adaptation for an integrated circuit includes receiving, by a workload prediction system of a hardware processor, telemetry data for one or more systems of the hardware processor. A workload prediction is determined by processing the telemetry data through a workload prediction model executed by a workload prediction controller of the workload prediction system. A profile is selected, from a plurality of profiles, that matches the workload prediction. The selected profile specifies one or more operating parameters for the hardware processor. The selected profile is provided to a power management controller of the hardware processor for controlling an operational characteristic of the one or more systems.
    Type: Grant
    Filed: March 8, 2023
    Date of Patent: March 25, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Julian Daniel John
  • Patent number: 12261350
    Abstract: A semiconductor device package is provided that includes a substrate, a first support structure disposed on the substrate and a first antenna. The first support structure includes a first surface spaced apart from the substrate by a first distance. The first antenna is disposed above the first surface of the first support structure. The first antenna has a first surface, a second surface opposite the first surface and a third surface extending from the first surface to the second surface, wherein the first surface and the second surface of the first antenna are exposed.
    Type: Grant
    Filed: August 8, 2023
    Date of Patent: March 25, 2025
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Guo-Cheng Liao, Yi Chuan Ding
  • Publication number: 20250096136
    Abstract: A disclosed semiconductor device includes (1) a silicon stack comprising a front-side Back-End-of-Line (BEOL) stack and a back side BEOL stack, the front-side BEOL stack comprising a plurality of signal routes and the back-side BEOL stack comprising a plurality of power delivery routes, and (2) a plurality of auxiliary power paths formed within the front-side BEOL stack and electrically coupled to the plurality of power delivery routes of the back-side BEOL stack via a plurality of programmable switches, the plurality of power delivery routes, the plurality of programmable switches, and the plurality of auxiliary power paths forming a programmable power delivery network (PDN). Various other apparatuses, systems, and methods of operation are also disclosed.
    Type: Application
    Filed: September 20, 2023
    Publication date: March 20, 2025
    Applicants: Advanced Micro Devices, Inc., Xilinx, Inc.
    Inventors: Divya Madapusi Srinivas Prasad, Gabriel H. Loh, Richard Schultz, Jeffrey Richard Rearick, Shidhartha Das, Suresh Ramalingam
  • Publication number: 20250093285
    Abstract: Provided is a subcellular self-tracer ion imaging and localization method of metal elements. Wherein, the above method includes: using the SEM-FIB-TOF-SIMS system to perform subcellular structure imaging and metal ion imaging on the sample slice, wherein in the SEM-FIB-TOF-SIMS system, the scanning electron microscope (SEM) is used to perform subcellular structure imaging on the sample slice; and the focused ion beam (FIB) is used to perform surface bombardment on the subcellular structures, and the secondary ions excited are detected by the time-of-flight secondary ion mass spectrometry (TOF-SIMS) to obtain the ion information in the analysis area and imaged.
    Type: Application
    Filed: December 3, 2024
    Publication date: March 20, 2025
    Applicant: Shandong Laboratory of Advanced Agricultural Sciences in Weifang
    Inventors: Xiaohua HUANG, Xing Wang DENG, Mengzhu CHENG, Jun ZHAO, Bin XU
  • Publication number: 20250098184
    Abstract: A method for increasing capacitance density within an integrated passive device can include forming a first trench capacitor within a substrate, forming a second trench capacitor within an insulating layer overlying the substrate, and connecting the first and second trench capacitors through connection vias that extend through the insulating layer to form an integrated passive device (IPD) capacitor. A high capacitance density device can include a stacked and co-integrated architecture of two or more tiers of trench capacitors.
    Type: Application
    Filed: September 20, 2023
    Publication date: March 20, 2025
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Arsalan Alam, Anadi Srivastava, Rajen Singh Sidhu, Alexander Helmut Pfeiffenberger, Liwei Wang
  • Publication number: 20250091318
    Abstract: A color conversion sheet according to the present invention includes a first wavelength conversion layer in which an organic phosphor is dispersed in a resin matrix, a first phosphor diffusion barrier layer positioned on one surface of the first wavelength conversion layer, and an adhesive layer positioned on one surface of the first phosphor diffusion barrier layer, wherein a Hildebrand solubility parameter of the first phosphor diffusion barrier layer satisfies a predetermined relationship between a Hildebrand solubility parameter of the resin matrix of the first wavelength conversion layer and a Hildebrand solubility parameter of a solvent contained in the first phosphor diffusion barrier layer, thereby resolving problems of changes in luminance characteristics and color change.
    Type: Application
    Filed: July 24, 2023
    Publication date: March 20, 2025
    Applicant: TORAY ADVANCED MATERIALS KOREA INC.
    Inventors: Sang Woo JIN, Jun Woo PARK, Ji Whan OH
  • Publication number: 20250096161
    Abstract: A method for increasing capacitance density within an integrated passive device can include forming a first trench capacitor within a first insulating layer overlying a substrate, forming a second trench capacitor within a second insulating layer overlying the first insulating layer, and connecting the first and second trench capacitors through connection vias that extend through the second insulating layer to form an integrated passive device (IPD) capacitor. A high capacitance density device can include a stacked and co-integrated architecture of two or more such layers.
    Type: Application
    Filed: September 20, 2023
    Publication date: March 20, 2025
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Arsalan Alam, Anadi Srivastava, Rajen Singh Sidhu, Alexander Helmut Pfeiffenberger, Liwei Wang
  • Publication number: 20250096073
    Abstract: An electronic device is disclosed. The electronic component has a front side and a backside opposite to the front side. The front side is configured to receive a first power. The backside is configured to receive a second power greater than the first power.
    Type: Application
    Filed: September 15, 2023
    Publication date: March 20, 2025
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chiung-Ying KUO, Jung Jui KANG, Hung-Chun KUO, Chun-Yen TING
  • Publication number: 20250093326
    Abstract: Method for evaluating cardiomyocytes using Raman scattering: a Raman spectrum of cardiomyocytes artificially induced to differentiate from pluripotent stem cells is acquired, an intensity of Raman-scattered light for a protein containing at least one of heme b and heme c as a prosthetic group is acquired from the Raman spectrum, and a state of progress of maturation of the cardiomyocytes is evaluated on the basis of the intensity of the Raman-scattered light. Method for evaluating differentiation into cardiomyocytes using Raman scattering: cells which are pluripotent stem cells are artificially induced to differentiate into cardiomyocytes, a Raman spectrum of the cells induced to differentiate is acquired, an intensity of Raman-scattered light for at least one of heme b and heme c is acquired from the Raman spectrum, and a state of progress of differentiation of the cells into cardiomyocytes is evaluated on the basis of the intensity of the Raman-scattered light.
    Type: Application
    Filed: January 12, 2023
    Publication date: March 20, 2025
    Applicants: OSAKA UNIVERSITY, National Institute of Advanced Industrial Science and Technology
    Inventors: Katsumasa Fujita, Kazuki Bando, Li Liu, Junjun Li, Yoshiki Sawa, Shigeru Miyagawa, Yasunori Nawa, Satoshi Fujita