Abstract: A memory package includes first, second, third, and fourth channels arranged consecutively in a clockwise direction on the memory package, each of the first, second, third, and fourth channels having access circuitry and memory arrays. In a first mode, the first channel controls access to the memory arrays in the second channel and the fourth channel controls access to the memory arrays in the third channel.

Abstract: A semiconductor device includes: a substrate having a first surface and a second surface opposite to the first surface; an electronic component disposed on the first surface of the substrate; a sensor disposed adjacent to the second surface of the substrate; an electrical contact disposed on the first surface of the substrate; and a package body exposing a portion of the electrical contact.

Abstract: A cell culture instrument configured to detach cells at a desired position and a cell processing method using the cell culture instrument. The cell culture instrument includes: a substrate; and a photoreactive layer having a photosolubility and a photothermal convertibility, wherein the photoreactive layer is laminated on the substrate, and the photoreactive layer includes a polymer having a photosolubility and a photothermal convertibility.

Abstract: Systems and methods for allocating computing resources within a distributed computing system are disclosed. Computing resources such as CPUs, GPUs, network cards, and memory are allocated to jobs submitted to the system by a scheduler. System configuration and interconnectivity information is gathered by a mapper and used to create a graph. Resource allocation is optimized based on one or more quality of service (QoS) levels determined for the job. Job performance characterization, affinity models, computer resource power consumption, and policies may also be used to optimize the allocation of computing resources.

Abstract: The disclosed device includes a memory-semantic fabric comprising memory components accessible by multiple processors and a controller for the memory-semantic fabric. The controller receives, from multiple processes, memory requests for a memory-semantic fabric. The controller also identifies, within the processes, a source process for each of the memory requests and prioritizes forwarding the memory requests to the memory-semantic fabric based on the source processes. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Concurrently with performing a visibility pass to generate visibility data for two or more bins of an image, a processing system determines whether a primitive to be rendered covers at least a predetermined threshold percentage of a tile of the image. In response to the primitive coving at least the predetermined threshold percentage of the tile, the processing system stores the depth data of the primitive in a depth buffer for pixel-based rendering. In response to the primitive not covering at least the predetermined threshold percentage of the tile, the processing system fuses the primitive with one or more preceding primitives sharing an edge with the primitive in the tile to generate a fused primitive. In response to the fused primitive being valid in the tile, the processing system passes the depth data of the fused primitive to the depth buffer.

Abstract: A magnetic sensor includes a magneto-sensitive body whose electromagnetic properties change under an action of an external magnetic field, a coil disposed to obtain an induced voltage proportional to the external magnetic field, a sampler configured to sample the induced voltage generated in the coil and obtains a sampling voltage, and an automatic correction circuit configured to relatively adjust a rise timing of a magneto-sensitive body clock for driving the magneto-sensitive body and a rise timing of a sampler clock for driving the sampler according to the sampling voltage.

Abstract: This disclosure describes systems, methods, and apparatus for generating a control signal for one or more actuators that is adjusted from a control signal dictated by setpoints, where the adjustment accounts for predicted delays and amplitude errors. More specifically, cross correlation between measurements of the actuator(s) outputs and time-shifted setpoints can be optimized for a time-shift that minimizes the cross correlation. The time-shifted setpoints along with the measurements can then be used to determine an amplitude difference and to remove noise from the amplitude difference. Dynamic uncertainty can then be found from this denoised data set and further optionally used to find the noise that was removed. The time delay, noise, and dynamic uncertainty can be used to preemptively adjust the control signal.

Abstract: The present invention provides a novel semiconductor device for high breakdown voltage having no drift layer.

Abstract: Power combiners and associated computer-implemented methods and computer program products are provided. An example power combiner includes a plurality of power input structures each of which defines a waveguide that receives a respective electromagnetic radiation input from a respective power source and a central combining conduit. The central combining conduit receives the respective electromagnetic radiation inputs communicated via respective power input structures and combines the respective electromagnetic radiation inputs into a combined power signal for output via an output port communicably coupled with the central combining conduit. The power combiner may also include a cooling loop configured to dissipate heat from at least one of the power input structures to an external environment of the power combiner.

Abstract: The present invention provides a microelectrode, comprising a flexible layer, an electrically conductive layer and a plurality of platinum dendrite structures, wherein the electrically conductive layer is arranged in the flexible layer, and wherein on the surface of the flexible layer are a plurality of grooves within which the electrically conductive layer is revealed partially, and wherein each of the groove is provided with one platinum dendrite structure therein. The plurality of grooves serve as focal electrodes distributed uniformly, with smaller electrode sites and more recording points. The modified platinum dendrite structures increase the surface area, electrical performance, biocompatibility and service life of the microelectrode. Besides, creating virtual electrodes by current steering technique increases the number of stimuli received by microelectrode during use, and improves its resolution in applications.

Abstract: Implementations of the present specification disclose a fare payment method, apparatus, and device. In one aspect, the method includes: receiving, at a terminal device supporting host-based card emulation (HCE), an HCE-based routing instruction from a fare collection device of a public transportation system; establishing, by the terminal device, a near field communication (NFC) connection with the fare collection device in response to the routing instruction; and transmitting, by the terminal device, payment-related information of a user of the terminal device to the fare collection device through the NFC connection, wherein the payment-related information is to be verified by the fare collection device, and wherein the fare collection device is configured to: verify the received payment-related information of the user; and in response to a successful verification, deduct a fare from an account of the user based on the payment-related information.

Abstract: Provided display panel includes a pixel circuit and a light emitting element. The pixel circuit includes a drive module, and a bias adjustment module; the drive module includes a drive transistor; and the bias adjustment module is configured to provide a bias adjustment signal to a first pole of the drive transistor or a second pole of the drive transistor. Operation modes of the display panel include a first mode and a second mode, and a brightness level of the display panel in the first mode is greater than a brightness level of the display panel in the second mode. The bias adjustment signal in the first mode is Vs1 and the bias adjustment signal in the second mode is Vs2, and where Vs1?Vs2.

Abstract: An image processing device or system, in particular for medical image processing, comprises an interface to receive image data, a storage system, and at least one integrated circuit operative to retrieve an image analysis model from the storage system, perform an image analysis that comprises applying the image analysis model to the image data to generate an image analysis output, generate an explainability signature for the image analysis, process at least the explainability signature to generate cross-check data indicative of a class prediction and/or a possible discrepancy in the image analysis, and initiate a control action that depends on the cross-check data.

Abstract: Systems and methods for operating a match network are disclosed. One match network comprises at least one first sensor to measure one or more first parameters and at least one second sensor to measure one or more second parameters. The match network also comprises means for assessing whether the match is operating as expected or operating outside of specifications using the one or more first-parameter measurements; the one or more second-parameter measurements; a setting of the match; or one or more expected parameter values.

Abstract: Systems, methods, and devices for integrated circuit power management. A mode of a power management state is entered, from the power management state, in response to an entry condition of the mode. A device that is otherwise powered off in the power management state is powered on in the mode of the power management state. In some implementations, the device includes a communications path between a second device and a third device. In some implementations, the device is in a power domain that is powered off in the power management state. In some implementations, the power domain is powered off in the mode. In some implementations, the device is powered on in the mode via a power rail that is specific to the mode. In some implementations, the entry condition of the mode includes an amount of data stored for display in a display buffer falling below a threshold amount.

Abstract: A semiconductor device package includes a carrier, an emitting element and a first package body. The carrier includes a first surface and a second surface opposite to the first surface. The emitting element is disposed on the first surface of the carrier. The first package body is disposed over the first surface of the carrier and spaced apart from the first surface of the carrier.

Abstract: An imaging device can provide an indication of a focus state of a displayed image to aid an operator to focus an image. The imaging device can include an image capture device configured form an image of a scene that includes an object viewed by the imaging device; a display to display the image the scene; a focus input to adjust a focus of the image displayed on the display; a hardware processor; and a memory storing computer-readable instructions, the instructions executable by the hardware processor to perform operations. The operations can include performing image processing on the image; determining a focus state of the image based on the image processing; and indicating a focus state of the image on the display.

Abstract: A semiconductor device package includes a redistribution layer, a plurality of conductive pillars, a reinforcing layer and an encapsulant. The conductive pillars are in direct contact with the first redistribution layer. The reinforcing layer surrounds a lateral surface of the conductive pillars. The encapsulant encapsulates the first redistribution layer and the reinforcing layer. The conductive pillars are separated from each other by the reinforcing layer.

Abstract: A system and method for efficiently creating layout for memory bit cells are described. In various implementations, a memory bit cell uses Cross field effect transistors (FETs) that include vertically stacked gate all around (GAA) transistors with conducting channels oriented in an orthogonal direction between them. The channels of the vertically stacked transistors use opposite doping polarities. The memory bit cell includes one of a read bit line and a write word line routed in no other metal layer other than a local interconnect layer. In addition, a six transistor (6T) random access data storage of the given memory bit cell consumes a planar area above a silicon substrate of four transistors.