Patents Assigned to ADVANCED
  • Patent number: 11917794
    Abstract: Separating temperature domains in cooled systems, including: cooling at least one first component of a circuit board using a first cooling system; and conductively coupling the at least one first component to at least one second component using a superconductive portion of a power plane of the circuit board.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: February 27, 2024
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Andrew G. Kegel, Jeffrey Bialozor
  • Patent number: 11912672
    Abstract: A novel compound having excellent light emission and heat stability is disclosed. Also disclosed is an organic electroluminescent device having properties such as light emitting efficiency, an operation voltage, and a service life improved by including the compound in at least one organic layer of the device.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: February 27, 2024
    Assignee: SOLUS ADVANCED MATERIALS CO., LTD.
    Inventors: Hyungchan Bae, Young Bae Kim, Hoe Moon Kim, Ho Jun Son, Jin Woong Kim
  • Patent number: 11915454
    Abstract: Various embodiments relate to a color palette for capturing a person's image for determination of a facial skin color, and a method and an apparatus using same. Various embodiments may provide a color palette, and a method and an apparatus using same, the color palette comprising: a central area which is provided to define a skin region in a facial image, and is empty or transparent; and a plurality of color areas which are provided to define a plurality of reference regions for use in determining a skin color of the skin region in the facial image, and arranged to surround the central area and disposed according to a rule determined on the basis of at least one color characteristic.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: February 27, 2024
    Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Hyeon-Jeong Suk, Yuchun Yan
  • Patent number: 11916004
    Abstract: An electronic device is provided. The electronic device includes a first carrier having a first surface, an interposer disposed over the first surface of the first carrier, wherein the interposer has a first thickness and a second thickness in a direction substantially perpendicular to the first surface of the first carrier; and a plurality of electrical connections between the first carrier and the interposer and configured to compensate a difference between the first thickness and the second thickness of the interposer.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: February 27, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Ching-Feng Cheng
  • Patent number: 11911805
    Abstract: An optical connector cleaning tool includes a fitting portion (44) fitted in the first or second hole (36, 37) of a connection component (32) into which a compact dual core optical connector is fitted on one end side and a cleaning medium (45) projecting from the fitting portion (44). The fitting portion (44) is formed to have a shape by which the fitting portion (44) is fitted in the first or second hole (36, 37) in each of the first and second postures as postures shifted through 180° with respect to as the center the middle (P2) of a virtual straight line connecting the centers of the two ferrules when viewed from an axial direction of the compact dual core optical connector. The fitting portion (44) contacts one ferrule in a state in which the fitting portion (44) is set in the first posture. The fitting portion (44) contacts the other ferrule in a state in which the fitting portion (44) is set in the second posture.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: February 27, 2024
    Assignees: NTT ADVANCED TECHNOLOGY CORPORATION, SENKO ADVANCED COMPONENTS, INC.
    Inventors: Etsu Hashimoto, Yoshiaki Haga, Kazutoshi Ando, Yohei Omodaka
  • Patent number: 11913132
    Abstract: A method for manufacturing a package includes generating an electric field between an anode and a cathode in an electroplating solution to electroplate a substrate electrically connected to the cathode; depositing metal on a central region of the substrate with a first deposition rate; depositing metal on an outer region of the substrate with a second deposition rate lower than the first deposition rate; and reducing the first deposition rate.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: February 27, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chia Chun Hsu, Chin-Feng Wang
  • Patent number: 11914609
    Abstract: The present disclosure provides a method for interconnecting a data lake and a relational database, including the following steps: S1: adding a data source class of a relational database to a data lake; S2: matching and using, by the data lake, a data source class of the relational database; and S3: determining and loading a corresponding driver according to the data source class, so as to connect the corresponding relational database. By cascading a data source registering configuration file, a relational database configuration file and a driver package catalog in a parameter passing method, when the data lake is started, a specific database to be used is designated unnecessarily, but a corresponding database is used directly. The configuration file is also traversed unnecessarily, but the user acquires configuration information as required in the parameter passing method.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: February 27, 2024
    Assignees: NANHU LABORATORY, BEIJING BIG DATA ADVANCED TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hao Liu, Tao Zhang, Lei Zhang, Peng Wang, Zhefeng Liu, Zhiling Chen, Qiuye Wang, Wei Chen, Yinlong Liu, Chenxi Yu
  • Patent number: 11915003
    Abstract: Disclosed are a process parasitism-based branch prediction method and device for serverless computing, an electronic device, and a readable storage medium. The method includes: receiving a calling request of a user for a target function; when capacity expansion is required, scheduling a container executing the target function to a new server that has not executed the target function in a preset period of time, wherein a parasitic process is pre-added to a base image of the container; triggering the parasitic process when the container is initialized on the new server, the parasitic process being used for initiating a system call, and triggering a system kernel to select a target template function according to the type of the target function and copying the target template function N times; using execution data of the copied N target template functions as training data to train a branch predictor on the new server.
    Type: Grant
    Filed: August 31, 2023
    Date of Patent: February 27, 2024
    Assignee: SHENZHEN INSTITUTES OF ADVANCED TECHNOLOGY
    Inventors: Kejiang Ye, Yanying Lin, Chengzhong Xu
  • Patent number: 11916227
    Abstract: A multilayer body is provided that is used as the negative electrode of a lithium-ion secondary battery that has a high capacity and is excellent in terms of safety, economic efficiency, and cycle characteristics. The multilayer body has a conductive substrate and a composite layer provided on the conductive substrate. The composite layer includes a plurality of particles of silicon oxide and a conductive substance present in gaps between the plurality of particles of silicon oxide. The average particle diameter of the particles of silicon oxide is 1.0 ?m or less. The multilayer body further has a conductive layer that is provided on the composite layer and contains a conductive substance. The conductive layer has a thickness of 20 ?m or less.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: February 27, 2024
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Mikito Mamiya, Junji Akimoto
  • Patent number: 11914517
    Abstract: Methods and apparatus provide monitoring of memory access traffic in a data processing system by tracking, such as by data fabric hardware control logic, a number of cache line accesses to a page of memory associated with one or more memory devices, and producing spike indication data that indicates a spike in cache line accesses to a given page of memory. Pages are moved from a slower memory to a faster memory based on the spike indication data. In some implementations, the tracking is done by updating a cache directory with data representing the tracked number of cache line accesses.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: February 27, 2024
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Sergey Blagodurov, Marko Scrbak, Brandon K. Potter
  • Patent number: 11915627
    Abstract: A viewing angle expansion plate, which is a multi-pinhole mask, includes a plurality of cell areas; and a plurality of pinholes formed in the plurality of cell areas, wherein each cell area from among the plurality of cell areas corresponds to a respective pixel from among a plurality of pixels in a flat panel display. The flat panel display includes a light source configured to emit parallel light; a flat panel, on which the parallel light is incident, configured to provide a three-dimensional image; and the viewing angle expansion plate.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: February 27, 2024
    Assignees: SAMSUNG ELECTRONICS CO., LTD., KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Wontaek Seo, Yongkeun Park, Hoon Song, Jungkwuen An, Jongchan Park
  • Publication number: 20240059605
    Abstract: A low dielectric sealing glass powder for a miniature radio-frequency glass insulator is made of the following raw materials expressed in molar percentages: SiO2: 70.5-74.0%, B2O3: 20.5-23.5%, Ga2O3: 0.5-2.0%, P2O5: 0.25-2.0%, Li2O: 0.4-6.0%, K2O: 0.1-1.5%, LaB6: 0.05-1.0%, and NaCl: 0.03-0.3%. The raw material components are simple, and the preparation method is easy to implement. The dielectric constant and dielectric loss of the prepared glass powder are low, and the melting and molding temperature is low, which are convenient for large-scale industrial production. The melting and molding temperature of the low dielectric sealing glass powder ranges from 1320° C. to 1360° C., and the obtained glass has a dielectric constant ranging from 3.8 to 4.1 and a dielectric loss ranging from 4×10?4 to 10×10?4 at a frequency of 1 MHz, and a sealing temperature ranging from 900° C. to 950° C.
    Type: Application
    Filed: April 24, 2022
    Publication date: February 22, 2024
    Applicant: CNBM RESEARCH INSTITUTE FOR ADVANCED GLASS MATERIALS GROUP CO., LTD
    Inventors: Shou PENG, Chong ZHANG, Weiwei WANG, Changqing LI, Jinwei LI, Xiaofei YANG, Gang ZHOU, Zhenkun KE, Xin CAO, Chuanli SHAN, Jia NI, Jiedong CUI, Fengyang ZHAO, Zhaojin ZHONG, Pingping WANG, Qiang GAO, Na HAN, Lifen SHI, Yong YANG
  • Publication number: 20240059706
    Abstract: A novel organic luminescent compound and an organic electroluminescent device using the novel organic luminescent compound are disclosed. The organic luminescent compound has excellent thermal stability, electrochemical stability, light emitting ability, and electron transport ability. An organic electroluminescent device includes one or more organic layers each including the organic luminescent compound and shows improved properties, for example, luminous efficiency, driving voltage, and service life characteristics.
    Type: Application
    Filed: December 14, 2021
    Publication date: February 22, 2024
    Applicant: SOLUS ADVANCED MATERIALS CO., LTD.
    Inventors: Jeongkeun PARK, Minsik EUM, Jaeyi SIM, Doshik KIM
  • Publication number: 20240060065
    Abstract: The present invention relates to a microorganism with increased carbon monoxide availability and use thereof.
    Type: Application
    Filed: October 11, 2022
    Publication date: February 22, 2024
    Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Byung-Kwan CHO, Sangrak JIN, Seulgi KANG, Jiyun BAE, Hyeonsik LEE
  • Patent number: 11908781
    Abstract: At least some embodiments of the present disclosure relate to a semiconductor package structure. The semiconductor package structure includes a substrate with a first surface, an encapsulant, an electronic component, and a patterned conductive layer. The encapsulant is disposed on the first surface of the substrate. The encapsulant includes a first surface and a second surface. The patterned conductive layer extends on the first surface and the second surface of the encapsulant and protrudes from the first surface and the second surface of the encapsulant. The electronic component is disposed on the patterned conductive layer.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: February 20, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wei-Chih Cho, Chun-Hung Yeh, Tsung-Wei Lu
  • Patent number: 11907812
    Abstract: A data generating method includes: an atomic model generating step of generating one or more three-dimensional atomic models corresponding to a nanomaterial to be measured; a three-dimensional data generating step of generating three-dimensional atomic level structure volume data corresponding to the nanomaterial to be measured based on the one or more three-dimensional atomic model; a tilt series generating step of generating a tilt series by simulating three-dimensional tomography for a plurality of different angles in a predetermined angle range for at least some of the three-dimensional atomic level structure volume data; and a three-dimensional atomic structure tomogram volume data generating step of generating a three-dimensional atomic structure tomogram volume data set by performing three-dimensional reconstruction on at least some of the three-dimensional atomic level structure volume data based on the tilt series.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: February 20, 2024
    Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Yongsoo Yang, Juhyeok Lee, Chaehwa Jeong
  • Patent number: 11905431
    Abstract: The present invention is a polyimide varnish for conductor coating, which provides a polyimide varnish comprising: a polyamic acid solution prepared through polymerization of at least one dianhydride monomer and at least one diamine monomer in an organic solvent; an aromatic carboxylic acid having four or more carboxyl groups; an alkoxy silane coupling agent; and an antioxidant, wherein the polyimide varnish has a solid content of 15 to 38 wt % on the basis of the total weight thereof, and a viscosity at 23° C. of 500 to 9,000 cP, and the coated material prepared from the polyimide varnish has a degree of softening resistance of 520° C. or higher, and a breakdown voltage (BDV) of 8 kV/mm or higher.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: February 20, 2024
    Assignee: PI ADVANCED MATERIALS CO., LTD.
    Inventors: In Hwan Hwang, Ik Sang Lee, Jeong Yeul Choi
  • Patent number: 11907070
    Abstract: An integrated circuit includes one or more processing units that execute instructions that employ a register file, control logic creates a pre-startup register free list, prior to normal operation of at least one of the processing units, that includes a list of registers devoid of defective registers. In some implementations, no column and row repair information is provided to register file repair logic. In certain examples, the register file is configured as a repair-less register file. During normal operation of the one or more processing units, the integrated circuit employs the pre-startup register free list to select registers in a register file for the executing instructions. Associated methods are also presented.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: February 20, 2024
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Eric Busta, Michael L. Golden, Sean M. O′Mullan, James Wingfield, Keith A. Kasprak, Russell Schreiber, Michael Estlick
  • Patent number: 11908966
    Abstract: A solar module having on the front a cover plate with an outer surface and an inner surface is described. An optical interference layer for reflecting light within a predefined wavelength range is arranged on the inner surface. The inner surface and/or the outer surface have a patterned region. The patterned region has a height profile with hills and valleys, and a portion of the patterned region is composed of flat segments that are inclined relative to a plane of the cover plate.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: February 20, 2024
    Assignee: CNBM RESEARCH INSTITUTE FOR ADVANCED GLASS MATERIALS GROUP CO., LTD.
    Inventors: Rene Kalio, Joerg Palm, Jens Kullmann, Manuel Dias, Sven Ring
  • Patent number: 11908815
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes an antenna layer, a first circuit layer and a second circuit layer. The antenna layer has a first coefficient of thermal expansion (CTE). The first circuit layer is disposed over the antenna layer. The first circuit layer has a second CTE. The second circuit layer is disposed over the antenna layer. The second circuit layer has a third CTE. A difference between the first CTE and the second CTE is less than a difference between the first CTE and the third CTE.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: February 20, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang