Patents Assigned to ADVANCED
  • Patent number: 11726837
    Abstract: In some examples, thermal aware optimization logic determines a characteristic (e.g., a workload or type) of a wavefront (e.g., multiple threads). For example, the characteristic indicates whether the wavefront is compute intensive, memory intensive, mixed, and/or another type of wavefront. The thermal aware optimization logic determines temperature information for one or more compute units (CUs) in one or more processing cores. The temperature information includes predictive thermal information indicating expected temperatures corresponding to the one or more CUs and historical thermal information indicating current or past thermal temperatures of at least a portion of a graphics processing unit (GPU). The logic selects the one or more compute units to process the plurality of threads based on the determined characteristic and the temperature information. The logic provides instructions to the selected subset of the plurality of CUs to execute the wavefront.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: August 15, 2023
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Karthik Rao, Shomit N. Das, Xudong An, Wei Huang
  • Patent number: 11726918
    Abstract: Dynamically coalescing atomic memory operations for memory-local computing is disclosed. In an embodiment, it is determined whether a first atomic memory access and a second atomic memory access are candidates for coalescing. In response to a triggering event, the atomic memory accesses that are candidates for coalescing are coalesced in a cache prior to requesting memory-local processing by a memory-local compute unit. The atomic memory accesses may be coalesced in the same cache line or atomic memory accesses in different cache lines may be coalesced using a multicast memory-local processing command.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: August 15, 2023
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Johnathan Alsop, Alexandru Dutu, Shaizeen Aga, Nuwan Jayasena
  • Patent number: 11728260
    Abstract: A wiring structure and a method for manufacturing the same are provided. The wiring structure includes a lower conductive structure, an upper conductive structure and a conductive via. The lower conductive structure includes a first dielectric layer and a first circuit layer in contact with the first dielectric layer. The upper conductive structure is attached to the lower conductive structure. The upper conductive structure includes a plurality of second dielectric layers, a plurality of second circuit layers in contact with the second dielectric layers, and defines an accommodating hole. An insulation material is disposed in the accommodating hole. The conductive via extends through the insulation material, and electrically connects the lower conductive structure.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: August 15, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Patent number: 11728252
    Abstract: A semiconductor device package includes a first conductive base, a first insulation layer and a second insulation layer. The first conductive base has a first surface, a second surface opposite to the first surface and a lateral surface extended between the first surface and the second surface. The lateral surface includes a first portion adjacent to the first surface and a second portion adjacent to the second surface. The first insulation layer comprises a first insulation material. The first insulation layer has a first surface and a second surface opposite to the first surface. The first insulation layer covers the first portion of the lateral surface of the first conductive base. The second insulation layer comprises a second insulation material and covers the second portion of the lateral surface of the first conductive base. The first insulation material is different from the second insulation material.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: August 15, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hui Hua Lee, Chun Hao Chiu, Hui-Ying Hsieh, Kuo-Hua Chen, Chi-Tsung Chiu
  • Patent number: 11727363
    Abstract: A system and method for verifying waste fulfillment events in the absence of human intervention using the input of one or more vehicle sensor inputs, one or more waste disposal cycle inputs, and GPS information to augment or supplement optical scanning technology such as RFID tags is disclosed.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: August 15, 2023
    Assignee: ADVANCED CUSTOM ENGINEERED SYSTEMS & EQUIPMENT COMPANY
    Inventor: Christopher M. Flood
  • Patent number: 11728282
    Abstract: A package structure includes a wiring structure, a first electronic device, a second electronic device and a reinforcement structure. The wiring structure includes at least one dielectric layer, and at least one circuit layer in contact with the dielectric layer. The at least one circuit layer includes at least one interconnection portion. The first electronic device and the second electronic device are electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the at least one interconnection portion of the at least one circuit layer. The reinforcement structure is disposed above the at least one interconnection portion of the at least one circuit layer.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: August 15, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Syu-Tang Liu, Min Lung Huang, Huang-Hsien Chang, Tsung-Tang Tsai, Ching-Ju Chen
  • Patent number: 11723713
    Abstract: A cutting element for an electrosurgical device. The cutting element includes an elongate non-conductive body having a first face opposite a second face, the first face and the second face defining an edge there between. A conductive element is disposed only along the edge, the conductive element being configured to cut tissue with monopolar radiofrequency energy.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: August 15, 2023
    Assignee: MEDTRONIC ADVANCED ENERGY LLC
    Inventors: Nathaniel R. Lau, Christopher Barden, Jessica Sacks, William X. Siopes
  • Publication number: 20230250567
    Abstract: A method of making a bespoke knitted compression garment. The method comprises providing a representation of a body part on which the compression garment is to be worn (S102), the representation comprising a plurality of datapoints. A desired pressure configuration to be applied by the compression garment on the body part is determined (S104). Representation courses around the representation are defined (S106). Sets of datapoints for each representation course are selected (S107). A curve for each set of datapoints and a circumference value of each curve is calculated (S108, S109). A pressure to be applied by each course is determined (S111) and a material for knitting, and a number of needles for each representation course, is determined based on the course pressure of the associated material course, a strain characteristic of the material, and the circumference value of the associated curve (S112). A garment is knitted according to the number of needles and the material (S113, S114).
    Type: Application
    Filed: July 9, 2021
    Publication date: August 10, 2023
    Applicant: ADVANCED THERAPEUTIC MATERIALS LIMITED
    Inventors: Adam Harwood, Clive Gunther, Najmal Hassan Chaudhury, James Sopper
  • Publication number: 20230253061
    Abstract: The present invention relates to a mechanical interconnect memory, and more particularly, to a mechanical interconnect memory applicable to smart interconnect technology that reduces the power consumption of an interconnect layer. A mechanical interconnect memory according to an embodiment of the present invention comprises: an upper electrode including: a spring part having at least one upward protruding portion between both ends of the spring part; and a moving part having one end of the moving part fixed to the at least one upward protruding portion of the spring part and the other end of the moving part being a free end of the moving part that is capable of moving up and down; and a lower electrode at least partially disposed under the moving part.
    Type: Application
    Filed: September 23, 2022
    Publication date: August 10, 2023
    Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Jun-Bo YOON, Yong-bok Lee, Pan-kyu Choi, Su-hyun Kim, Tae-Soo Kim
  • Patent number: 11721884
    Abstract: A semiconductor device package is provided that includes a substrate, a first support structure disposed on the substrate and a first antenna. The first support structure includes a first surface spaced apart from the substrate by a first distance. The first antenna is disposed above the first surface of the first support structure. The first antenna has a first surface, a second surface opposite the first surface and a third surface extending from the first surface to the second surface, wherein the first surface and the second surface of the first antenna are exposed.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: August 8, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Guo-Cheng Liao, Yi Chuan Ding
  • Patent number: 11722220
    Abstract: A system including optical devices is provided. The system includes a first substrate and a first device for optical communication. The first device has a first surface, a second surface opposite to the first surface, and a first side contiguous with the first surface and the second surface. Moreover, the first side is smaller than one of the first surface and the second surface in terms of area. The first device is attached at the first side thereof to the first substrate.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: August 8, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chang-Yu Lin, Cheng-Yuan Kung, Hung-Yi Lin
  • Patent number: 11718828
    Abstract: The present invention concerns a method for obtaining an implantable cartilage gel for tissue repair of hyaline cartilage, comprising particles of chitosan hydrogel and cells that are capable of forming hyaline cartilage, said method comprising a step for amplification of primary cells in a three-dimensional structure comprising particles of physical hydrogel of chitosan or a chitosan derivative, then a step for re-differentiation and induction of the synthesis of extracellular matrix by said amplified cells, in the same three-dimensional structure, wherein said cells are primary articular chondrocytes and/or mesenchymal stem cells differentiated into chondrocytes. The present invention also concerns the cartilage gel obtained thereby, and its various uses for cartilage repair following a traumatic lesion or an osteoarticular disease such as osteoarthritis.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: August 8, 2023
    Assignee: ADVANCED CHITOSAN SOLUTIONS BIOTECH
    Inventors: Pascale Hazot, Frédéric Mallein Gerin
  • Patent number: 11718807
    Abstract: A hydrophilic slippery treatment agent which allows for the formation of a coating having hydrophilicity concurrently with water droplet removability via drying at lower temperatures, a surface treatment method using the hydrophilic slippery treatment agent, a substrate having a hydrophilic slippery coating formed thereon by the surface treatment method, and a fin material for a heat exchanger having a hydrophilic slippery coating formed thereon by the surface treatment method are provided. The treatment agent contains an organosilicon compound with a specific structure including both a hydrophilic-chain-containing group and a hydrolyzable group, and a metal alkoxide.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: August 8, 2023
    Assignees: NIPPON PAINT SURF CHEMICALS CO., LTD, NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Souhei Kaneko, Masaki Matsuzaki, Atsushi Hozumi, Chihiro Urata
  • Patent number: 11721652
    Abstract: A semiconductor device package includes an electronic component and a substrate. The electronic component has a first surface and a second surface. The substrate is connected to the first surface of the electronic component through an adhesive layer. The substrate includes a first antenna disposed over the second surface of the electronic components through the adhesive layer.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: August 8, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 11720572
    Abstract: One embodiment provides a method and system for recommending content to users. During operation, the system can select a content piece from a content library and extract, by a computer using a natural language processing (NLP) technique, one or more keywords from the content piece. The system can determine a domain associated with the content piece based on the extracted keywords and obtain domain knowledge of the determined domain. The system can generate a feature tag for the content piece based on the extracted keywords and the obtained domain knowledge, and generate an attribute tag for a user based on historical data associated with the user. The system can then recommend one or more content pieces from the content library to the user based on feature tags associated with the one or more content pieces and the attribute tag for the user.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: August 8, 2023
    Assignee: ADVANCED NEW TECHNOLOGIES CO., LTD.
    Inventor: Yangyang Liu
  • Patent number: 11721782
    Abstract: The present disclosure relates to a light detection device including: a substrate 100; a lower electrode 200 formed on the substrate; an organic semiconductor layer 300 formed on the lower electrode 200; and an upper electrode 400 formed on the organic semiconductor layer 300, wherein a Schottky contact is formed at least one of a junction between the organic semiconductor layer and the lower electrode or a junction between the organic semiconductor layer and the upper electrode.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: August 8, 2023
    Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Kyoung Sik Yu, Yeong Hoon Jin, Hyung Suk Kim, Seung Hyup Yoo
  • Patent number: 11721645
    Abstract: A semiconductor package device includes a wiring structure, a semiconductor chip and an encapsulant. The semiconductor chip is electrically connected to the wiring structure. The encapsulant is disposed on the wiring structure and covers the semiconductor chip. A roughness (Ra) of a surface of the encapsulant is about 5 nm to about 50 nm.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: August 8, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 11721678
    Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: August 8, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Mei Huang, Shih-Yu Wang, I-Ting Lin, Wen Hung Huang, Yuh-Shan Su, Chih-Cheng Lee, Hsing Kuo Tien
  • Patent number: 11721384
    Abstract: Hardware-assisted Dynamic Random Access Memory (DRAM) row merging, including: identifying, by a memory controller, in a DRAM module, a plurality of rows storing identical data; storing, in a mapping table, data mapping one or more rows of the plurality of rows to another row; and excluding the one or more rows from a refresh the DRAM module.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: August 8, 2023
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Jagadish B. Kotra
  • Patent number: 11717279
    Abstract: A modular surgical retractor including a handle and a blade. The handle includes a base and a neck. The neck projects from an end of the base to a tail region. The blade includes a head section and a blade member. The head section includes opposing side walls and a floor combining to define a slot sized to receive the neck. The blade member projects from the head section. The blade is removably attached to the handle. In some embodiments, a light source, such as an LED, is disposed within the neck and arranged to emit light along a face of the blade member. Two or more additional blades are provided, each additional blade including the head section and a differently configured blade member.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: August 8, 2023
    Assignee: MEDTRONIC ADVANCED ENERGY LLC
    Inventors: Roger D. Greeley, Jonathan J. Barry, David Hubelbank, Ryan Kelley