Abstract: A thermoplastic resin composition includes (A) a graft rubber copolymer, (B) an aromatic vinyl-vinyl cyanide-based copolymer, and (C) a silicone-modified aromatic vinyl-vinyl cyanide-based copolymer. The silicone-modified aromatic vinyl-vinyl cyanide-based copolymer (C) has an average particle size of about 100 ?m or less.
Type:
Grant
Filed:
June 23, 2015
Date of Patent:
January 2, 2018
Assignee:
Lotte Advanced Materials Co., Ltd.
Inventors:
Bo Eun Kim, Joo Hyun Jang, Jae Won Heo, Kwang Soo Park, Yu Jin Jung, Young Sub Jin
Abstract: A hard surface cleaning composition which provides a shine to hard surfaces and which is water resistant includes 0.001-50 wt. % of at least one detersive surfactant, at least 10 wt. % of a diluent, the diluent including water, and 0.01-40 wt. % of particles comprising at least one of an anionic polyurethane polymer and an anionic polyurethane hybrid polymer, formed as an aqueous dispersion, the particles having an average particle size of less than 170 nm.
Type:
Grant
Filed:
August 26, 2013
Date of Patent:
January 2, 2018
Assignee:
Lubrizol Advanced Materials, Inc.
Inventors:
Dennis N. Malaba, Feng-Lung Gordon Hsu, Jeffrey A. Fruscella, Smita Brijmohan
Abstract: In various embodiments, an illumination apparatus features spatially separated input and output regions, a light source, a phosphor for light conversion, and an out-coupling structure.
Abstract: Techniques to maintain gain flatness in the frequency response of a passband signal over a circuit chain. The techniques may be employed in the receive chain of a millimeter wave band wireless receiver, in the transmit chain of a millimeter wave band wireless transmitter, or in both the receive chain and the transmit chain of a millimeter wave band wireless transceiver. The techniques include mismatching the input and output impedance of a passive low pass filter used in the chain to peak the gain of the passband signal at or near the cutoff frequency (Fc) of the filter.
Type:
Grant
Filed:
August 28, 2014
Date of Patent:
January 2, 2018
Assignees:
ADVANCED MICRO DEVICES, INC., AMD FAR EAST LTD.
Abstract: A semiconductor device includes a substrate, a passivation layer and an optical element. The substrate includes a surface and a sidewall. The passivation layer is disposed on the surface of the substrate. The optical element is disposed in the substrate and exposed from the sidewall of the substrate. The sidewall of the substrate is inclined towards the surface of the substrate at an angle of approximately 87 degrees to approximately 89 degrees.
Type:
Grant
Filed:
January 13, 2017
Date of Patent:
January 2, 2018
Assignee:
ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Inventors:
Yi-Min Chin, Jia-Hao Zhang, Chi-Han Chen, Mei-Ju Lu
Abstract: It discloses a vanadium-titanium compound material with high thermal stability and high activity and a preparation method thereof. The vanadium-titanium compound material is mainly composed of vanadium oxide and titanium oxide, where the content of vanadium oxide is 0.5% to 30% by mass of the vanadium-titanium compound material, and the crystal form of titanium oxide in the vanadium-titanium compound material is one of anatase and TiO2(B) or a mixture thereof.
Abstract: Disclosed decoding method of the intra prediction mode comprises the steps of: determining whether an intra prediction mode of a present prediction unit is the same as a first candidate intra prediction mode or as a second candidate intra prediction mode on the basis of 1-bit information; and determining, among said first candidate intra prediction mode and said second candidate intra prediction mode, which candidate intra prediction mode is the same as the intra prediction mode of said present prediction unit on the basis of additional 1-bit information, if the intra prediction mode of the present prediction unit is the same as at least either the first candidate intra prediction mode or the second candidate intra prediction mode, and decoding the intra prediction mode of the present prediction unit.
Type:
Grant
Filed:
November 29, 2016
Date of Patent:
January 2, 2018
Assignees:
Electronics and Telecommunications Research Institute, Korea Advanced Institute of Science and Technology
Inventors:
Jong Ho Kim, Hui Yong Kim, Se Yoon Jeong, Sung Chang Lim, Ha Hyun Lee, Jin Ho Lee, Suk Hee Cho, Jin Soo Choi, Jin Woong Kim, Chie Teuk Ahn, Mun Churl Kim, Bum Shik Lee
Abstract: Legacy bus operations, such as x86 I/O instructions having an address space separate from memory address space, are supported in a system in which I/O devices are coupled to a microcontroller connected via an SPI bus or other bit-serial bus. Each legacy bus operation is recognized and trapped by an interface controller, such as a south-bridge controller, which maps the trapped legacy bus operation into a corresponding bit-serial bus transaction, and transacts this corresponding bit-serial bus transaction on the bit-serial bus. Existing software infrastructure using x86 I/O instructions can remain intact, with I/O transactions bound for the SPI bus.
Abstract: Systems and methods for assessing compliance with position therapy. In an embodiment, position therapy is provided to a user while the user is wearing a position therapy device. The position therapy comprises, by the device, collecting positional data, determining positions of the user over a time period based on the positional data, and, when it is determined that the user is in a target position, providing feedback to the user to influence the user to change to a non-target position. In addition, the device stores a duration of use in its memory. The duration of use indicates a duration that the user has used the wearable position therapy device in each of one or more positions. An assessment of the user's compliance with the position therapy is then provided based, at least in part, on the duration of use.
Type:
Grant
Filed:
June 24, 2014
Date of Patent:
January 2, 2018
Assignee:
Advanced Brain Monitoring, Inc.
Inventors:
Daniel J. Levendowski, Timothy Zavora, Philip R. Westbrook, Mirko Mitrovic, Bratislav Veljkovic, Chris Berka, Jonny Trejo
Abstract: Provided are: an alkali metal titanium oxide having a uniform composition and that is such that there are no residual by-products having a different composition or unreacted starting materials; and a method for producing a titanium oxide and proton exchange body obtained by processing the alkali metal titanium oxide. The method produces an alkali metal titanium oxide by firing the result of impregnating the surface and inside of pores of porous titanium compound particles with an aqueous solution of an alkali metal-containing component. The alkali metal titanium oxide is subjected to proton exchange, and with the proton exchange body of the alkali metal titanium oxide as the starting material, the titanium oxide is produced through a heat processing step.
Type:
Grant
Filed:
August 14, 2014
Date of Patent:
January 2, 2018
Assignees:
NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, ISHIHARA SANGYO KAISHA, LTD.
Abstract: A computer-implemented method for determining whether a video frame is of a 3D TB type (Top-Bottom) or a 3D LR type (Left-Right) frame, characterized in that it comprises the steps of: receiving a video frame (100); extracting at least three portions (121-124) of the frame, each portion belonging to a distinct quarter of the frame (100, 120) and being positioned at the same fragment of the quarter; calculating color histograms for each portion (121-124); comparing the color histograms of at least two different pairs of portions; generating a frame type indicator based on the result of comparison of the color histograms.
Abstract: A process for etching a substrate comprising polycrystalline silicon to form silicon nanostructures includes depositing metal on top of the substrate and contacting the metallized substrate with an etchant aqueous solution comprising about 2 to about 49 weight percent HF and an oxidizing agent.
Type:
Grant
Filed:
October 27, 2015
Date of Patent:
January 2, 2018
Assignee:
Advanced Silicon Group, Inc.
Inventors:
Brent A. Buchine, Marcie R. Black, Faris Modawar
Abstract: A cooling system is provided for a 3D integrated circuit (IC) to deliver fluid in x, y, and z dimensions to interior regions of the IC as a means to regulate heat. An IC includes a microfluidic network of channels, at least one sensor and at least one microelectromechanical system (MEMS)-based device that is disposed within the network of channels and that is configured to regulate a flow of fluid within the network of channels. Each sensor monitors a state of the IC. Each MEMS-based device receives control signals based on a state of the IC and regulates a flow of fluid within the network of channels based on control signals that area received on a real-time basis based on changes detected in a state of the IC.
Type:
Application
Filed:
June 24, 2016
Publication date:
December 28, 2017
Applicant:
Advanced Micro Devices, Inc.
Inventors:
Alexander D. Breslow, Dong Ping Zhang, Nuwan Jayasena
Abstract: A method and apparatus for scheduling instructions of a shader program for a graphics processing unit (GPU) with a fixed number of registers. The method and apparatus include computing, via a processing unit (PU), a liveness-based register usage across all basic blocks in the shader program, computing, via the PU, the range of numbers of waves of a plurality of registers for the shader program, assessing the impact of available post-register allocation optimizations, computing, via the PU, the scoring data based on number of waves of the plurality of registers, and computing, via the PU, the number of waves for execution for the plurality of registers.
Type:
Application
Filed:
June 23, 2016
Publication date:
December 28, 2017
Applicant:
Advanced Micro Devices, Inc.
Inventors:
Robert A. Gottlieb, Christopher L. Reeve, Michael John Bedy
Abstract: Described is a system and method for using virtual vector register files. In particular, a graphics processor includes a logic unit, a virtual vector register file coupled to the logic unit, a vector register backing store coupled to the virtual vector register file, and a virtual vector register file controller coupled to the virtual vector register file. The virtual vector register file includes a N deep vector register file and a M deep vector register file, where N is less than M. The virtual vector register file controller performing eviction and allocation between the N deep vector register file, the M deep vector register file and the vector register backing store dependent on at least access requests for certain vector registers.
Type:
Application
Filed:
June 23, 2016
Publication date:
December 28, 2017
Applicants:
Advanced Micro Devices, Inc., ATI Technologies ULC
Inventors:
Ljubisa Bajic, Michael Mantor, Syed Zohaib M. Gilani, Rajabali M. Koduri
Abstract: A method and apparatus for reducing TLB shootdown operation overheads in accelerator-based computing systems is described. The disclosed method and apparatus may also be used in the areas of near-memory and in-memory computing, where near-memory or in-memory compute units may need to share a host CPU's virtual address space. Metadata is associated with page table entries (PTEs) and mechanisms use the metadata to limit the number of processing elements that participate in a TLB shootdown operation.
Abstract: A number of ladar sensors, visible cameras, and traffic signal lights are mounted within a traffic control zone, and a local traffic controller is provided to ensure safety and provide optimum traffic flow for vehicular and pedestrian traffic by combining the inputs from the ladar sensors and visible cameras and detecting the type of traffic, the intended path, and then controlling the signal lights dynamically. The local traffic controller also maintains a local traffic database, and communicates via duplex radio link with similarly equipped vehicles to effect an additional control capability. A regional traffic controller communicates with the local traffic controller to provide control and optimal traffic flow within a district control zone, and maintains a district traffic database.
Abstract: The present invention provides a thermoplastic elastomer (TPE), in particular a polyurethane-based thermoplastic elastomer (TPU), that has exceptional elongation, strength, and wear resistance, and in particular has exceptional wear resistance. The present invention provides: a thermoplastic elastomer composition containing A) a thermoplastic urethane elastomer composition having A1) at least one polyol selected from the group consisting of polyether polyols, polyesterpolyols, and polycarbonate polyols, A2) a diisocyanate, and A3) a chain extender, and B) polyrotaxane formed by arranging blocking groups, at both ends of pseudo-polyrotaxane formed by inclusion of the openings of cyclic molecules in a shape skewered by linear molecules, so that the cyclic molecules are not eliminated; and a thermoplastic elastomer derived from this composition.
Abstract: Simultaneous expression of a plurality of foreign genes by using a stealthy RNA gene expression system that is a complex that does not activate the innate immune mechanism and is formed from an RNA-dependent RNA polymerase, a single-strand RNA binding protein, and negative-sense single-strand RNAs including the following (1) to (8): (1) a target RNA sequence that codes for any protein or functional RNA; (2) an RNA sequence forming a noncoding region and derived from mRNA; (3) a transcription initiation signal sequence recognized by the RNA-dependent RNA polymerase; (4) a transcription termination signal sequence recognized by the polymerase; (5) an RNA sequence containing a replication origin recognized by the polymerase; (6) an RNA sequence that codes for the polymerase; (7) an RNA sequence that codes for a protein for regulating the activity of the polymerase; and (8) an RNA sequence that codes for the single-strand RNA binding protein.
Type:
Application
Filed:
January 18, 2016
Publication date:
December 28, 2017
Applicants:
NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, TOKIWA-BIO INC.
Abstract: Described is a method and processing apparatus to improve power efficiency by gating redundant threads processing. In particular, the method for gating redundant threads in a graphics processor includes determining if data for a thread and data for at least another thread are within a predetermined similarity threshold, gating execution of the at least another thread if the data for the thread and the data for the at least another thread are within the predetermined similarity threshold, and using an output data from the thread as an output data for the at least another thread.
Type:
Application
Filed:
June 22, 2016
Publication date:
December 28, 2017
Applicants:
Advanced Micro Devices, Inc., ATI Technologies ULC
Inventors:
Syed Zohaib M. Gilani, Jiasheng Chen, QingCheng Wang, YunXiao Zou, Michael Mantor, Bin He, Timour T. Paltashev