Abstract: An event based test system for testing an IC device under test (DUT) designed under an automatic electronic design (EDA) environment. The event based test system includes an event memory for storing event data derived directly from simulation of design data for an intended IC in the EDA environment where the event data to denote each event is formed with time index indicating a time length from a predetermined point and an event type indicating a type of change at an event, an event generation unit for generating test vectors based on the event data where waveform of each vector is determined by the event type and a timing of the waveform is determined by accumulating the time index of previous events, and means for supplying test vectors to the DUT and evaluating response outputs of the DUT at predetermined timings.

Abstract: A recovery clock synchronized with an internal clock faster than a system clock is obtained with an edge timing of the system clock output from a DUT. The present invention includes: a time interpolator 20 which includes flip-flops (FF 21) which receive system clocks of the DUT 1, a delay circuit 22 which outputs time-series level data, from the FF 21, and an encoder 28 which receives the time-series level data output and encodes it into positional data indicative of an edge timing; a digital filter 40 which includes a plurality of registers 41 which sequentially store the positional data and output the positional data as a recovery clock; and a data side selector 30 which selects output data of the DUT 1 base on the recovery clock.

Abstract: There is provided a phase correction circuit capable of detecting a skew between a data signal and a clock signal without requiring a clock signal as pattern data upon initialization.

Abstract: A position detection apparatus detecting a position of a mark similar to a template image from an input image has a calculation block. The calculation block includes phase difference calculation means and mark position detection means. The phase difference calculation means calculates a phase difference between a phase component of each frequency component when the template image is transformed into frequency components and a phase component for each frequency component when an input image is transformed into frequency components with a reference point being set at a predetermined position on the input image. The phase component difference calculated by the phase difference calculation means is transformed into a phase impulse response function, according to which the mark position detection means detects the position of the mark on the input image.

Abstract: An electron beam exposure apparatus for exposing a wafer with an electron beam includes a section for generally controlling a wafer exposing system, a first buffer memory for temporarily storing exposure data, a second buffer memory for temporarily storing the exposure data, a first exposing section for irradiating the wafer with an electron beam based on exposure data output from the first buffer memory, and a first comparing section for comparing exposure data output from the first buffer memory with exposure data output from the second buffer memory and notifying the comparison results to the general control section. The exposure data stored in the first buffer memory and the exposure data stored in the second buffer memory are identical to one another when no error is involved. Further, an exposure apparatus and a pattern error detection method for accurately detecting an error of an exposure pattern formed to a wafer is disclosed.

Abstract: An electron beam exposure apparatus for exposing wafer with an electron beam, includes: a first electromagnetic lens system for making the electron beam incident substantially perpendicularly on a first plane be incident on a second plane substantially perpendicularly; a second electromagnetic lens system for making the electron beam that was substantially perpendicularly incident on the second plane be incident on the wafer substantially perpendicularly; a rotation correction lens provided within the first electromagnetic lens system for correcting rotation of the electron beam caused by at least the first electromagnetic lens system; a deflection system for deflecting the electron beam to a position on the wafer; and a deflection-correction optical system provided within the second electromagnetic lens system for correcting deflection aberration caused by the deflection system.

Abstract: There is provided a timing generator capable of absorbing a delay time error of a variable delay circuit without increasing the number of bits of path data and suppressing deterioration of the timing accuracy from the designed value to the minimum. The timing generator is configured to include a selection unit which assigns five-bit delay device candidates to a three-bit partial bit signal of all the bit signals constituting the path data outputted from a linearization memory and selects three delay devices whose number is equal to the bit count of the partial bit signal.

Abstract: A connector including a plug and a socket and a driving section for fitting the plug and the socket by moving the driving section in a first direction substantially perpendicular to the fitting direction of the socket and the plug. The driving section has a first groove part provided in the first direction, and a second groove part provided substantially perpendicular to the first direction. The plug has a first protruding portion engaging with the first groove part, and the socket has a second protruding portion engaging with the first groove part. When the driving section moves in the first direction, the driving section depresses the second protruding portion in the fitting direction at the second groove part to move the socket in the fitting direction, thus fitting the plug in the socket.

Abstract: This invention provides a semiconductor memory test system in which the test system will not conduct logic comparison for a particular memory block after a failure is detected in the block. The test system which tests writing and erasing as a unit of block in the memory under test. The test system includes a register provided for each memory under test for holding a first failure generated in a particular block at a first control signal from a pattern generator, establishes a pass result for the particular block for test cycles after the first failure, thereby treating any failure result for the particular block as the pass result thereafter; and resets the register at a cycle specified by a second control signal from the pattern generator to release the pass result.

Abstract: An optical pulse testing apparatus incorporating an optical pulse generator composed of low cost components. The optical pulse testing apparatus comprises: a ring optical path including an optical fiber 30 with a rare earth element added to; an excitation light source 32 which enters excitation optical pulses into the optical fiber 30; an optical branching filter 38 for branching the circulating optical pulses circulating through the ring optical path to emit output optical pulses; and a photodetector 40 for detecting the circulating optical pulses circulating through the ring optical path to obtain signals indicative of a light intensity and a generation timing of the circulating optical pulses. Thus, the optical pulse generator, and the optical pulse testing apparatus and method using the optical pulse generator require no expensive optical parts and complicated device control.

Abstract: An event pipeline and vernier summing apparatus for high speed event based test system processes the event data to generate drive events and strobe events with various timings at high speed to evaluate a semiconductor device under test. The event pipeline and vernier summing apparatus is configured by an event count delay logic, a vernier data decompression logic, an event vernier summation logic, an event scaling logic, and a window strobe logic. The event pipeline and summing method and apparatus of the present invention is designed to perform high speed event timing processing with use of a pipeline structure. The window strobe logic provides a function for detecting a window strobe request and generating a window strobe enable.

Abstract: A method of converting test vectors in an original cycle based test language into a target cycle based test language, by forming a set of templates depicting waveforms defined in the target test language, decomposing a waveform in the original test language into a set of constituent events where each event includes data showing at least a starting value and a number of subsequent edges of the waveform, comparing the template and the set of constituent events at different levels of abstraction determined in advance, in the order of a signal level, a wave kind level where the signal is configured by a plurality of wave kinds, and a character level where the wave kind is configured by a plurality of characters, and storing the waveform data in the target test language when a match is detected and retrieving corresponding parameters of the waveform in the original test language.

Abstract: A method of debugging an individual core in core based system-on-a-chip (SOC) ICs with high accuracy and observability, and a structure of SOC incorporating the method. The method includes the steps of building two or more metal layers of a pad frame for each core in an SoC while connecting I/O (input and output) pads on a lower metal layer to a top metal layer, thereby exposing all I/O pads and power pads on a surface of the top metal layer of the pad frame of each core, and applying test vector to each core through the I/O pads on the top metal layer of the core and evaluating response outputs of the core received through the I/O pads on the top metal layer.

Abstract: A delay circuit having an adjustable delay resolution is provided. The delay circuit has a path through which a signal transmits, a field effect transistor whose source region and drain region are connected to the path, and an impressed voltage control unit which controls a voltage to be impressed to the gate electrode of the field effect transistor. The impressed voltage control unit may be a digital analog converter.

Abstract: A method of evaluating a core based SoC detects and localizes faults in the cores or interconnects between the cores with high accuracy and observability. The method includes the steps of building two or more metal layers to create core I/O pads having all I/O pads and power pads on a surface of the top metal layer of the pad frame of each core, testing the SoC as a whole by applying test vectors to the SoC through chip I/O pads and evaluating response outputs of the SoC, testing each core in the SoC by applying core specific test vectors to the core through the core I/O pads on the top metal layer of the core and evaluating response outputs of the core, and finding a location of a fault when the fault is detected when testing the SoC chip as a whole or when testing each of the cores.

Abstract: A time shift circuit for changing a delay timing of a portion of a test pattern for testing a semiconductor device. The time shift circuit includes a multiplexer for selectively producing delay value data indicating a value of time shift in response to a shift command signal, a vernier delay unit for producing timing vernier data based on the delay value data selected by the multiplexer, and a timing generator for generating a timing edge for the specific portion of the test pattern based on the timing vernier data from the vernier delay unit. The shift command signal sets either a normal mode where predetermined delay value data is selected by the multiplexer or a time shift mode where delay value data for shifting the timing edge in real time is selected by the multiplexer.

Abstract: A pattern generator for semiconductor test system for testing a semiconductor memory device by generating and applying test patterns. The pattern generator is capable of freely generating inversion request signals for inverting the read/write data for specified memory cells for a memory device under test having different total numbers of memory cells between X (row) and Y (column) directions. The locations of specified memory cells are on a diagonal line on an array of memory cells in the memory device under test or on a reverse diagonal line which is perpendicular to the diagonal line.

Abstract: A contact structure for establishing electrical connection with contact targets. The contact structure is formed of a contactor carrier and a plurality of contactors attached to a contactor carrier. The contactors are inserted in diagonal through holes on the contactor carrier and attached to the contactor carrier through adhesives. The contactor has a top end having a flat top surface, a straight diagonal beam integral with the top end and configured by an upper beam portion and a lower beam portion, and a lower end at an end of the lower beam portion to contact with a contact target. A length of the upper beam portion and a length of the lower beam portion are about the same. A probe contact assembly using the contact structure is also disclosed which incorporates a flip chip bonding technology to interconnect the components therein.

Abstract: There is disclosed a semiconductor test apparatus enabling writing into an information write space of a block including a failure cell into which block writing is inhibited partially or entirely by the bad block mask function and the fail loop back function. A pattern generation block outputs to an output controller a release signal (S4) for releasing the write inhibit instruction defined by an inhibit signal (S3) and a mask signal (SI). When the output controller receives the release signal (S4), the output controller outputs a write enable signal (WE) to an MUT (4).

Abstract: A driver circuit for switching an output voltage (Vout) at an output terminal 3 by using diode bridges 1 and 2 includes a first current mirror circuit 10 for letting flow a first balance current I2e and letting flow a first transition current I2f obtained by adding a first stationary current to a product of the first balance current I2e and a predetermined multiplier when switching from the low level to the high level, and a second current mirror circuit 20 for letting flow a second transition current I2h obtained by adding a second stationary current to a product of the second balance current I2g and a predetermined multiplier when switching from the high level to the low level. As a result, the power dissipation in the stationary state is reduced without lowering the slew rate at the time when switching the output voltage.