Abstract: A measurement apparatus comprising a serial resistor in series with an element under measurement; a switching section that sequentially selects ends of a serial circuit including the element under measurement and the serial resistor, and ends of the serial resistor; an applying section that applies an application voltage or application current corresponding to a preset setting value, to each of the sequentially selected ends; a measuring section that, for each of the sequentially selected ends, measures current when the applying section applies the application voltage corresponding to the setting value and measures voltage when the applying section applies the application current corresponding to the setting value; and a resistance calculating section that calculates the resistance value of the element under measurement, based on either the setting values set sequentially in the applying section or measured values measured sequentially by the measuring section for each of the sequentially selected ends.

Abstract: A server stores multiple configuration data. A tester hardware is configured to be capable of changing at least a part of its functions according to configuration data stored in rewritable nonvolatile memory, to supply a power supply voltage to a DUT, to transmit a signal to the DUT, and to receive a signal from the DUT. An information technology equipment is configured such that, (i) when the test system is set up, the information technology equipment acquires the configuration data from the server according to the user's input, and writes the configuration data to the nonvolatile memory. Furthermore, the information technology equipment is configured such that, (ii) when the DUT is tested, the information technology equipment executes a test program so as to control the tester hardware, and to process data acquired by the tester hardware.

Abstract: An existing test head is made best use of and a capital investment is reduced. A test apparatus for testing a plurality of devices under test includes: a plurality of test heads for retaining therein at least one test board to test devices under test; a connecting section mounted on upper surfaces of the plurality of test heads and is independently fixed to each of the plurality of test heads; and a DUT board on which the plurality of devices under test are mounted, the DUT board being mounted to the connecting section, where the at least one test board is mountable and removable through a side surface of each of the plurality of test heads while the connecting section is mounted to the test head.

Abstract: A system for testing a device under test (DUT) can include: a test controller unit that includes a first memory is operable to store a data pattern; a bridge circuit that includes a second memory that is smaller than the first memory, and a functional unit that includes a third memory that is smaller than the second memory. Portions of the data pattern can be selectively transferred from the first memory to the second memory during and for DUT testing operations. The functional circuit can interface with the DUT for testing. Portions of the data pattern can be selectively transferred from the second memory to the third memory for application to the DUT.

Abstract: A switching apparatus that switches a connection state between two terminals, comprising a switch that switches the connection state between the two terminals according to a control voltage supplied thereto; a first power supply section that generates power supply voltage with a first voltage value; a second power supply section that generates power supply voltage with a second voltage value; and a driving section that, upon receiving switching instructions to switch the switch from a first state to a second state, uses power generated by the first power supply section to change the control voltage to be the first voltage value, and then uses power generated by the second power supply section to further change the control voltage from the first voltage value to the second voltage value, in the same direction and with a rate of change over time that is less than a rate of change over time used when changing to the first voltage value.

Abstract: A method according to one embodiment of the present invention for evaluating test results for a memory module. The method comprises reviewing contents of a test data stream for one or more sections of the memory module. A first counter is incremented when a defective portion is encountered in the test data stream for a first section of the one or more sections of the memory module. Each defective portion of the first section is marked as good in the test data stream so long as a first counter value is equal to or below a first threshold value. Data from the test data stream identifying defective portions of the first section are stored in an error cache for each remaining defective portion of the first section identified after the first counter passes a first threshold value.

Abstract: An apparatus for providing a distributed and scalable number of power supplies used in automatic test equipment. The apparatus includes at least one Pin Electronics (PE) module comprising a plurality of PE channels. The apparatus includes at least one programmable power supply (PPS) module comprising a plurality of programmable power supply channels, wherein the at least one PPS module is remote from the at least one PE module. That apparatus includes a test site controller executing a test program comprising a plurality of test instructions delivered over the plurality of Pin Electronics (PE) channels and the plurality of programmable power supply (PPS) channels in order to test a plurality of devices under test (DUTs) in parallel.

Abstract: A test board can be inserted to a test head and removed from the test head while the connecting section for mounting thereon devices under test is mounted on the upper portion of the test head. A test head for retaining therein at least one test board for testing devices under test, includes: a casing provided with, on one side surface thereof, an opening through which the at least one test board is inserted and removed, the casing retaining therein the at least one test board with an upper side thereof oriented towards an upper surface of the casing; and a mounting member that guides a lower side of the at least one test board through the opening to a pre-set position, imposes an upward force to the lower side of the at least one test board, thereby mounting the at least one test board to the casing.

Abstract: A microelectronic contactor assembly can include a probe head having microelectronic contactors for contacting terminals of semiconductor devices to test the semiconductor devices. A stiffener assembly can provide mechanical support to microelectronic contactors and for connecting a probe card assembly to a prober machine. A stiffener assembly may include a main body and a plurality of mounting points, wherein at least one of the mounting points is flexibly connected to the main body by one or more laterally extending beams that has a section modulus normal to the lateral direction significantly greater than in the lateral direction. The stiffener assembly allows for differential thermal expansion of various components of the microelectronic contactor assembly while minimizing accompanying dimensional distortion that could interfere with contacting the terminals of semiconductor devices.

Abstract: A pattern printing apparatus comprising an ink output section including a nozzle that drops ink and a heating section that heats a preheating target region; a driving section that moves the substrate relative to the ink output section; and a control section that controls the driving section. The control section causes the substrate to move relative to the ink output section such that the preheating target region is positioned in a progression path of the drawing target region and causes a pattern formed by the ink to be drawn, and when switching an extension direction of the pattern being drawn, the control section causes the preheating target region to move to an end portion of the pattern drawn before the switching and causing the preheating target region to be heated.

Abstract: An apparatus includes a plurality of test heads to which probe cards are electrically connected; a wafer tray which is able to hold a semiconductor wafer; and an alignment apparatus which positions the semiconductor wafer held on the wafer tray relatively with respect to the probe card so as to make the wafer tray face the probe card. The wafer tray has a pressure reducing mechanism which pulls the wafer tray toward the probe card. The alignment apparatus is configured to be able to move along the array direction of the test heads.

Abstract: A calibration module for a tester, for testing a device under test, includes a pair of RF-channel terminals, a calibration device, a pair of measurement terminals and a mode selector. The pair of RF-channel terminals is configured to send or receive measurement signals to or from an RF-channel of the tester. The calibration device is configured to perform a calibration of the RF-channel based on the measurement signals sent to, or received from, the RF-channel. The pair of measurement terminals is configured to send or receive measurement signals to or from the device under test. The mode selector is configured to connect, in a calibration phase, the pair or RF-channel terminals to the calibration device for calibrating the RF-channel and to connect, in a measurement phase, the pair of RF-channel terminals to the pair of measurement terminals for routing measurement signals from the RF-channel to the device under test or vice versa.

Abstract: ATE performs testing of memory devices with distributed processing operations. A redundancy analysis (RA) system has a first test site processor (TSP), operable for controlling a testing routine over multiple DUTs and analyzing redundancy data returned from a first of the DUTs. The RA has at least a second TSP, operable for analyzing redundancy data returned from a second of the DUTs. The RA may have one or more additional TSPs, each operable for analyzing redundancy data returned from an additional DUT. Controlling the testing routine includes directing the RA in each of the first and second (and any of the additional) TSPs.

Abstract: A light measurement apparatus includes a master laser, a slave laser, an illumination light pulse, and a signal-under-measurement generator. The master laser generates as an output a master laser light pulse, and the slave laser generates as an output a slave laser light pulse having a repetition frequency or a phase different from that of the master laser light pulse. The illumination light pulse generator receives the master laser light pulse and generates as an output an illumination light pulse, and the signal-under-measurement generator, at a point in time when receiving a light pulse under measurement obtained by illuminating the object under measurement with the illumination light pulse and further the slave laser light pulse, generates as an output a signal under measurement according to a power of the light pulse under measurement. The apparatus corrects an error in a measurement of the signal under measurement.

Abstract: An ATE system performs RA over NAND flash memory DUTs. A first UBM captures fresh failure related data from a DUT. A second UBM transmits existing failure related data. A fail engine accesses the stored existing failure related data and generates a failure list based thereon. The storing and the accessing the existing failure related data, and/or the generating the failure list, are performed in parallel contemporaneously in relation to the capturing the fresh data. The generated failure list is queued. A failure processor, which may be operable for controlling the capturing, computes a redundancy analysis based on the queued failure list. The first and second UBMs then ping-pong operably.

Abstract: An electron beam exposure method includes the steps of: preparing an exposure mask having a plurality of opening patterns formed by dividing a drawing object pattern into exposable regions; and drawing the drawing object pattern by performing exposure with an electron beam passing through the opening patterns of the exposure mask. Each end portion serving as a joint in each opening pattern of the exposure mask is provided with a joining portion tapered in a width of the opening pattern. The exposure is performed in such a way that portions drawn through adjacent joining portions overlap each other.

Abstract: Example features or aspects of the present invention are described in relation to a small, quiet integrated cooling system for an apparatus for testing electronic devices. Characteristics of the test apparatus including a low noise output, low power consumption and a compact size with a small spatial and volume footprint are selected for deployment and use in a an office like environment. The test apparatus comprises a chassis frame and a cooler frame disposed within the chassis frame and thus integrated within the test apparatus, which has a reduced form factor suitable for the in-office deployment.

Abstract: The present invention relates to a method for adjusting transitions in a bit stream of a signal to be evaluated by comparison with a predetermined expected bit stream, comprising the steps of receiving said bit stream signal by a transition adjustment filter, providing a transition frame signal to said transition adjustment filter, said transition frame signal providing information for eliminating non-deterministic clock latencies within said bit stream of said received signal, and adjusting said bit stream of said received signal according to said transition frame signal resulting in an adjusted bit stream being in alignment to said expected bit stream.

Abstract: There is provided an electronic device transfer apparatus which has an excellent capacity of transferring DUTs between trays. An electronic device transfer apparatus, which transfers DUTs between trays, includes a device conveying unit. The device conveying unit includes a plurality of shuttles which hold the DUTs, an endless first guide rail which guides the shuttles, and first to third feeders which move the shuttles on the first guide rail. The shuttles are movable on the first guide rail over the entire circumference of the rail.

Abstract: Serial input devices (e.g., pin electronics modules) are coupled to an interface via data lines, clock lines, and select lines. A first subset and a second subset of the devices are each arrayed in columns, rows, and layers. Each data line is coupled to a respective row in the first subset and a respective row in the second subset; each clock line is coupled to a respective column in the first subset and a respective column in the second subset; and each layer in each subset is coupled to a respective select line. The interface can program a device by concurrently activating one of the data lines, one of the clock lines, and one of the select lines.