Abstract: To manufacture a switching apparatus that includes a piezoelectric actuator with increased lifespan, provided is a method for manufacturing a bimorph actuator, comprising first piezoelectric element layer formation of forming a first piezoelectric element layer on a substrate; support layer formation of forming a support layer made of an insulator on the first piezoelectric element layer; second piezoelectric element layer formation of forming a second piezoelectric element layer on the support layer; and removal of removing a portion of the substrate to form an actuator that includes the first piezoelectric element layer, the support layer, and the second piezoelectric element layer.

Abstract: Disclosed herein is a cost effective, efficient, massively parallel multi-wafer test cell. Additionally, this test cell can be used for both single-touchdown and multiple-touchdown applications. The invention uses a novel “split-cartridge” design, combined with a method for aligning wafers when they are separated from the probe card assembly, to create a cost effective, efficient multi-wafer test cell. A “probe-card stops” design may be used within the cartridge to simplify the overall cartridge design and operation.

Abstract: Automated testing system and method of testing memory devices with distributed processing operations. A redundancy analysis system includes multiple test site processors (TSPs) respectively coupled to multiple devices under test (DUTs). Each TSP is installed with a redundancy analyzer configured to analyzing redundancy data returned from a respective (DUT). Each TSP may be coupled with a respective fail engine for returning the redundancy data from the corresponding DUT. A main TSP of the multiple TSPs is configured to control testing routine over the multiple DUTs and process failure related data from the DUTs. The main TSP may direct the RAs distributed in the multiple TSPs to execute the redundancy analyzers in parallel.

Abstract: A measurement auxiliary circuit is configured to form a resonance circuit together with a detection target. An ATAC is coupled with the resonance circuit. A signal generator applies an AC probe signal VS to the resonance circuit. After the impedance measurement apparatus enters a stable state, an impedance detection unit measures a voltage at at least one node and/or a current that flows through at least one current path. The impedance detection unit detects the impedance of the detection target based on the measurement value.

Abstract: Provided is an electronic device handling apparatus capable of increasing the number of simultaneous measurements while suppressing the increase in cost. An electronic device handling apparatus, which moves bare dies relative to a probe card, includes: a thermal head which includes a plurality of holding regions each of which holds the bare die and has openings; at least one lift unit which is movably held by the thermal head so as to correspond to the holding regions and is able to advance and retreat through the openings; a moving device which moves the thermal head; and a fixed arm which is able to support the one lift unit.

Abstract: An apparatus for testing a device. The apparatus comprises a test control module and a test analysis module. The test control module is operable to generate and transmit first prober and handler (PH) requests to a supervisor module. The supervisor module is operable to transmit first PH commands to a prober and handler for execution thereof. The test analysis module is operable to generate and transmit second PH requests to the supervisor module. The supervisor module is further operable to transmit second PH commands to the prober and handler for execution thereof. The execution of the second PH commands are performed transparently to the test control module.

Abstract: In one embodiment, a semiconductor test control system includes a computer system having a plurality of hardware resources; a hypervisor installed on the computer system; and a test floor controller installed on the computer system. The hypervisor virtualizes the hardware resources and provides each of at least one virtual appliance with access to a respective virtual set of the hardware resources. Each virtual set of the hardware resources places its respective virtual appliance in controlling communication with at least a first aspect of a semiconductor test system, thereby enabling the respective virtual appliance to test a respective type of semiconductor device. The test floor controller is in controlling communication with i) at least a second aspect of the semiconductor test system, and ii) each of the at least one virtual appliance.

Abstract: A handler for conveying a plurality of devices under test to a socket for a test that can reduce a test time includes: a test section provided with the socket; a heat applying section into which a tray having a plurality of devices under test placed on its surface is conveyed and that controls the temperature of the devices under test to a predetermined test temperature and conveys the tray into the test section; a device image capturing section that in the heat applying section, captures images of the respective devices under test by moving with respect to the surface of the tray in two non-parallel directions of a first direction and a second direction; and a position adjusting section that adjusts the positions of the devices under test with respect to the socket based on the images of the devices under test captured by the device image capturing section.

Abstract: A power supply apparatus supplies a power supply signal to a device's power supply terminal via a power supply line. An A/D converter receives, via a feedback line, an analog measurement value corresponding to the power supply signal supplied to the device's power supply line, and converts the analog measurement value into a digital measurement value. A digital calculation unit generates a control value by digital calculation such that the digital measurement value from the A/D converter matches a predetermined reference value. A D/A converter digital/analog converts the control value so as to supply the analog power supply signal to the device's power supply terminal via the power supply line. A feedback ratio calculation unit calculates the ratio between the control value and the digital measurement value. The digital calculation unit is configured to change its calculation content based on the ratio calculated by the feedback ratio calculation unit.

Abstract: To realize a wireless communication apparatus with high transceiver coil mounting density, provided is a wireless communication apparatus comprising a plurality of differential coil pairs that respectively transmit and receive differential signals to and from a plurality of external differential coil pairs, through magnetic coupling, wherein one coil in a first differential coil pair among the differential coil pairs is provided at a distance from each of two coils of a second differential coil pair among the differential coil pairs that is less than or equal to a distance between the two coils of the second differential coil pair, and the other coil of the first differential coil pair is provided at a distance from each of the two coils of the second differential coil pair that is greater than the distance between the two coils of the second differential coil pair.

Abstract: A tester system is disclosed. The tester system comprises a tester module operable to generate test signals for testing a plurality of DUTs. It also comprises a plurality of cables operable to communicatively couple the tester module with a tray comprising the plurality of DUTs through a thermal chamber wall interface. Further, it comprises a plurality of connectors in contact with the tray, wherein the plurality of connectors is operable to provide an interface between the plurality of cables and conductive traces on the tray, and further wherein each of the plurality of connectors is operable to pass a respective subset of the test signals to each DUT on the tray via the conductive traces.

Abstract: An automatic tester, comprising a first signal converter, a first signal path, and a second signal path. The first signal converter is operable to convert, using a conversion clock signal, a signal from a digital signal domain to an analog signal domain to acquire an analog stimulus signal. The first signal path is operable to forward the analog stimulus signal from the first signal converter to a second signal converter operable to convert the analog stimulus signal back from the analog signal domain to the digital signal domain. The second signal path is operable to forward one of the conversion clock signal and a signal derived thereof from the first signal converter to the second signal converter. A difference between a propagation delay of an analog stimulus signal in response to a clock cycle of the conversion clock signal via the first signal path and a propagation delay of the conversion clock signal of the clock cycle via the second signal path is within a predetermined tolerance range.

Abstract: An adaptive thermal control system maintains and regulates an accurate and stable thermal environment for a device under test. The adaptive thermal control system includes (i) pre-trigger communications from automatic test equipment (ATE) to automatic thermal control (ATC) allowing slow-responding ATC to start responding to an imminent thermal change before the thermal change occurs, (ii) a control profile which indicates to the ATC, prior to anticipated thermal change, that a change is imminent and the nature of the change over time. The generation and fine-tuning of the control profile can be done by two different methods (i) with the semi-automatic approach the tester does some pre-tests in order to determine a typical response profile which the test program then adjusts using adaptive techniques, (ii) With the fully automatic adaptive circuitries same typical response profile is algorithmically adjusted and utilized to control the ATC.

Abstract: Provided is a handler apparatus which can connect devices under test to sockets of a test apparatus quickly and with low power consumption. The handler apparatus for conveying and connecting a plurality of devices under test to a plurality of sockets provided on a test head of a test apparatus, includes a position adjusting section that moves each of the plurality of devices under test on the test tray and adjusts the position thereof to a corresponding one of the plurality of sockets; and a device mounting section that mounts the plurality of devices under test whose positions have been adjusted by the position adjusting section, to the plurality of sockets.

Abstract: A system for testing a device under test (DUT) includes a test controller unit that includes a first memory operable to store a data pattern; a bridge circuit that includes a second memory that is smaller than the first memory, and a functional unit that includes a third memory that is smaller than the second memory. Portions of the data pattern are selectively transferred from the first memory to the second memory during and for DUT testing operations. The functional circuit interfaces with the DUT for testing. Portions of the data pattern are selectively transferred from the second memory to the third memory for application to the DUT.

Abstract: A method for testing a device-under-test includes receiving, from at least one test channel circuit dedicated to communicate with an input/output pin of the device-under-test by means of at least one hardware resource, at least one logical control command describing a desired operation of the at least one hardware resource, and converting, by means of a resource controller, the at least one logical control command into at least one dedicated control command for the at least one hardware resource, wherein the at least one dedicated control command is adapted to be received by a physical implementation of the at least one hardware resource.

Abstract: A method for using shared pins in a concurrent test execution environment is disclosed. The method relates to scheduling tests in concurrently executing test flows for automated test equipment (ATE) in a way so that resources can be shared between the test flows. The method comprises determining if any of a plurality of splits used by a first test contains at least one resource that is shared, wherein the first test and a second test are sequenced for execution in two separate concurrently executing test flows. The method further comprises determining if the first test should execute before the second test if the split is associated with resources required by both the second and first tests. Finally the method comprises reserving the split containing the at least one shared resource for access by the first test before beginning execution of the first test.

Abstract: A method for performing test site synchronization within automated test equipment (ATE) is presented. The method comprises controlling a plurality of test program controllers (TPCs) using a plurality of bridge controllers (BCs), wherein each TPC can initiate multiple asynchronous events. For an asynchronous event initiated by a TPC, raising a busy flag while the asynchronous event is not yet complete and de-asserting the busy flag when the asynchronous event is complete, wherein the asynchronous event corresponds to a task requiring an indeterminate amount of time. It also comprises generating a busy signal in the first BCs in response to receiving a busy flag from any of the plurality of TPCs, wherein the busy signal remains asserted while any of the plurality of TPCs asserts a busy flag. Finally, it comprises transmitting the busy signal to the plurality of TPCs, wherein the TPCs use the busy signal to synchronize operations.

Abstract: A synchronization pattern generating unit generates a synchronization pattern required for a clock recovery unit which has been built into a DUT to maintain a link with an external circuit. A gate signal generating unit generates a gate signal which is asserted in a period in which a vector pattern is to be supplied to the DUT. In a first mode, a pattern selecting unit is configured such that it outputs the vector pattern during a period in which the gate signal is asserted and outputs a fixed output level during a period in which the gate signal is negated. In a second mode, the pattern selecting unit is configured such that it outputs the vector pattern during a period in which the gate signal is asserted and outputs the synchronization pattern during a period in which the gate signal is negated.

Abstract: Disclosed herein is a scan optimizer system and method designed to generate optimal ATE input/output timing with small margin but yielding stable results. Therefore the scan test time is greatly improved.