Abstract: A first integrated circuit design with a first maximum operating frequency is modified to achieve a second integrated circuit design with a second maximum operating frequency. The integrated circuit design comprises an arrangement of cells. Each of these cells drives a signal that propagates through a net of other circuit elements to one or more nodes that are limited by respective signal timing constraints. An analytical cost function is assigned to each of the cells. Each analytical cost function comprises a value for its respective cell that is based on one or more speed-related factors indicative of the impact of the respective cell on the first maximum operating frequency of the first integrated circuit design. One or more of the cells are replaced with different cells based on the determined analytical cost functions.

Abstract: Various systems and methods for tri-column code based error reduction are disclosed herein. For example, a digital information system is disclosed that includes channel detector. Such a channel detector receives an encoded data set and provides an output representing the encoded data set. The exemplary system further includes a decoder that receives the first output and is operable to perform three slope parity checks on the received first output. In turn, the decoder provides another output representing the encoded data set.

Abstract: The invention, in one aspect, provides a method for fabricating a semiconductor device. In one aspect, the method provides for a dual implantation of a tub of a bipolar transistor. The tub in bipolar region is implanted by implanting the tub through separate implant masks that are also used to implant tubs associated with MOS fabricate different voltage devices in a non-bipolar region during the fabrication of MOS transistors.

Abstract: Disclosed is a circuit configured to apply a supply voltage to a switching element (e.g., a transistor). The circuit includes a latch and a processor. The latch is configured to sample a voltage of an output signal of the switching element, and the processor is configured to generate a power adjustment signal to adjust the supply voltage based on the voltage sampled by the latch.

Abstract: Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. In another aspect, warping of an integrated circuit device comprising at least one die attached to a base is controlled by applying a counterbalancing layer to at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die.

Abstract: A method and apparatus of reorganizing cells received over data communication lines at a receive node is provided. The cells have an initial order identified by monotonically increasing sequence identifiers. The receive node has buffers associated with respective ones of the communication lines. Each of the buffers has an output position. A cell having a smallest sequence identifier is detected from one or more cells at the output positions of the buffers. It is determined if the smallest sequence identifier is sequentially consecutive to a specified sequence identifier. If the smallest sequence identifier is sequentially consecutive to the specified sequence identifier, the cell having the smallest sequence identifier is dequeued from an output position of one of the buffers and the specified sequence identifier is redefined as the smallest sequence identifier.

Abstract: Remote control code filtering techniques are disclosed that are suitable for use in a remote control code relaying system. A portion of a received remote control code is compared with corresponding portions of stored remote control codes. The received remote control code can be filtered based on the comparison. The filtering can comprise outputting the received remote control code or a portion thereof, discarding the received remote control code, or adding a new remote control code to the stored remote control codes. The remote control code can be received from a network or from a hardware interface (e.g., which converts an electromagnetic remote control signal to the remote control code). The received remote control code can be output to a network or to a hardware interface for subsequent transmission of an electromagnetic remote control signal. Filtering can occur before or after the network.

Abstract: The invention relates flash memory programming techniques. An object of the invention is to provide a flash memory programming technique avoiding problems of the known state of the art and in particular, saving a significant amount of time during the development and/or production phases of any equipment containing flash memory devices and also saving time during an updating or upgrading procedure of such an equipment already being in use. Accordingly, the invention proposes for programming a flash memory device to program only differences in information between data already stored in the flash memory device and new data to be stored.

Abstract: Disclosed is an audio device that adjusts the cadence of played songs. A user sensor determines cadence data based on movement of the user. A desired cadence is determined based on the cadence data received from the sensor. The cadence of songs is determined by low pass filtering digital representations of the songs and determining the period (T) of the back beat of the songs. An adjustment of the period (T) of the songs is then determined such that the adjustment of the period (T) of the songs results in the songs having the desired cadence. The period (T) of the back beat of the subsequent songs are then adjusted.

Abstract: A system including an event monitor for monitoring at least one transmission link. Each event monitor receives transmission link addresses from an address sequencer and transmits related event data to a centralized storage register. The address sequencer also transmits the addresses to the storage register. The event monitor compares new event data for each address with old event data stored by the event monitor. If a difference is detected, the event monitor sends a strobe signal to the storage register, which stores the event data reflecting the difference and the related address data. The strobe signal is also sent to a signaling device, which sends an interrupt signal to cause a microprocessor to read the event and address data from the storage register. Optionally, the signaling device does not send an interrupt signal until a threshold number of strobe signals have been received.

Abstract: Disclosed is a system and method for a clock and data recovery (CDR) circuit. A phase selection circuit (PSC) generates a signal comprising frequency and phase. A voltage controlled oscillator (VCO) connected to the PSC generates a clock signal. The clock signal controls the frequency of the signal. The CDR circuit also includes a phase adjustment signal generator connected to the PSC for generating a phase adjustment signal. The phase adjustment signal controls the phase of the signal.

Abstract: A method and apparatus for the implementation of reduced state sequence estimation is disclosed, with an increased throughput using precomputation (look-ahead), with only a linear increase in hardware complexity with respect to the look-ahead depth. The present invention limits the increase in hardware complexity by taking advantage of past decisions (or survivor symbols). The critical path of a conventional RSSE implementation is broken up into at least two smaller critical paths using pipeline registers. Various reduced state sequence estimation implementations are disclosed that employ one-step or multiple-step look-ahead techniques to process a signal received from a dispersive channel having a channel memory.

Abstract: Remote analysis method and system for Home Phoneline Networks (HPNs), i.e., local area networks made up of telephone wiring in residential premises. In such a network connected to the Internet, a host computer collects measurements of the frequency response of the local network as well as values of addresses and other important network parameters of devices also located on the local network. The results of this data collection, having been sent via the Internet, may be displayed within a web browser on a remote computer external to the local network in a web. This data can then be monitored conveniently by a service technician or the like at any location.

Abstract: A virtual segmentation system and a method of operating the same. In one embodiment, the virtual segmentation system includes a protocol data unit receiver subsystem configured to (i) receive at least a portion of a protocol data unit and (ii) store the at least a portion of the protocol data unit in at least one block, and a virtual segmentation subsystem, associated with the protocol data unit receiver subsystem, configured to perform virtual segmentation on the protocol data unit by segmenting the at least one block when retrieved without reassembling an entirety of the protocol data unit.

Abstract: In one embodiment, a method for determining whether an encoded message in a shared channel is not intended for a communications device. The method includes: (a) decoding the message to recover a multi-bit codeword; (b) determining whether the codeword is valid or invalid, wherein, if the codeword is determined to be invalid, then the encoded message is not intended for the communications device; and (c) if the codeword is determined to be valid, then performing one or more other steps of the method to determine whether the encoded message in the shared channel is not intended for the communications device.

Abstract: A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. Generally, the integrated circuit structure includes a semiconductor layer with a major surface formed along a plane thereof and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. In one embodiment of the invention, a semiconductor device includes a first layer of semiconductor material and a first field-effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The integrated circuit further includes a capacitor having a bottom plate, dielectric layer and a top capacitor plate.

Abstract: A system for improving the attenuation of an undesired signal found in a differential signal path through the use of inductive coupling. The system includes a primary inductor, a secondary inductor, and a filter. The primary inductor and the secondary inductor operably couple an input differential signal pair to an output differential signal pair, and the filter attenuates an undesired signal in the output differential signal pair.

Abstract: A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A first group of the transistors are formed during formation of a triple well for use in providing triple well isolation for complementary metal oxide semiconductor field effect transistors also formed on the semiconductor substrate. Additional bipolar junction transistors with different collector doping densities are formed during a second doping step after forming a gate stack for the field effect transistors. Implant doping through bipolar transistor emitter windows forms bipolar transistors having different doping densities than the previously formed bipolar transistors.

Abstract: 3D sound is generated using an improved HRTF modeling technique for synthesizing HRTFs with varying degrees of smoothness and generalization. A plurality N of spatial characteristic function sets are regularized or smoothed before combination with corresponding Eigen filter functions, and summed to provide an HRTF (or HRIR) filter having improved smoothness in a continuous auditory space. A trade-off is allowed between accuracy in localization and smoothness by controlling the smoothness level of the regularizing models with a lambda factor. Improved smoothness in the HRTF filter allows the perception by the listener of a smoothly moving sound rendering free of annoying discontinuities creating clicks in the 3D sound.

Abstract: In some examples, a protocol accelerator extracts a queue identifier from an incoming packet, for identifying a first buffer queue in which the packet is to be stored for transport layer processing. A packet having an error or condition is identified, such that the accelerator cannot perform the processing on that packet. A processor is interrupted. The identified packet is stored in a second buffer queue. The processor performs transport layer processing in response to the interrupt, while the accelerator continues transport layer processing of packets in the first buffer queue. In some examples, a TCP congestion window size is adjusted. A programmable congestion window increment value is provided. The window size is set to an initial value at the beginning of a TCP data transmission. The window size is increased by the increment value when an acknowledgement is received.