Abstract: In one embodiment, a receiver including one or more signal-processing blocks and a hardware-based matrix co-processor. The one or more signal-processing blocks are adapted to generate a processed signal from a received signal. The hardware-based matrix co-processor includes two or more different matrix-computation engines, each adapted to perform a different matrix computation, and one or more shared hardware-computation units, each adapted to perform a mathematical operation. At least one signal-processing block is adapted to offload matrix-based signal processing to the hardware-based matrix co-processor. Each of the two or more different matrix-computation engines is adapted to offload the same type of mathematical processing to at least one of the one or more shared hardware-computation units.

Abstract: A system (10) for monitoring and controlling a fabrication process includes at least a first subsystem (12), a crystallographic analysis subsystem (14), and a second subsystem (16), wherein the first subsystem and second subsystem perform respective fabrication steps on a workpiece. The crystallographic analysis subsystem may be coupled to both the first subsystem and second subsystem. The analysis subsystem acquires crystallographic information from the workpiece after the workpiece undergoes a fabrication step by the first subsystem and then provides information, based on the crystallographic information acquired, for modifying parameters associated with the respective fabrication steps. The system may also include neural networks (24, 28) to adaptively modify, based on historical process data (32), parameters provided to the respective fabrication steps. The analysis subsystem may include a electromagnetic source (61), a detector (66), a processor (67), a controller (68) and a scanning actuator (65).

Abstract: An electronic device includes a metallic conducting lead having a surface. A pre-solder coating over the surface consists essentially of tin and one or more dopants selected from Al or a rare earth element.

Abstract: Digital correction of multibit ADAC nonlinearities for error feedback DACs is provided. The integral nonlinearity (INL) error of the multibit ADAC is estimated (on line or off line) by a low-resolution calibration ADC (CADC) and stored in a random-access memory (RAM) table. The INL values are then used to compensate for the ADAC's distortion in the digital domain. When this compensation is combined with mismatch-shaping techniques such as DWA, the resolution requirement for CADC can be relaxed significantly. The implementation of the proposed correction circuit for error-feedback modulators is inherently simple, since the correction only needs a digital summation without any additional digital filtering.

Abstract: Methods and apparatus for use with an integrated circuit device of a processing device of a network node of a digital networking system, configured to monitor one or more control messages received at the processing device from each of a plurality of CPE devices, and limiting the one or more control messages to one or more specified rates for a specified duration. The integrated circuit device is further configured to provide one or more data channels to the plurality of CPE devices from the processing device in response to the one or more control messages processed at the processing device.

Abstract: Various systems and methods for generating and/or ordering error indications are disclosed herein. In some cases, the error indication is used as an erasure pointer in a memory access system. As one particular example, a system for ordering erasure pointers is disclosed that includes a group of N sort cells, where N is a whole number. Each of the sort cells is operable to maintain a respective error indication that includes an error value and an associated error pointer. Further, the group of N sort cells is operable to receive an incoming error indication including error value and associated error pointer, and to update the error indication of one or more of the group of N sort cells based in part on the incoming error value. The system also includes a selector circuit that is operable to allow selectable access to each of the respective error pointers maintained in the group of N sort cells.

Abstract: A compensation circuit for reducing power consumption in at least one digital circuit includes a first sample circuit connected to a first supply voltage, a second sample circuit connected to a second supply voltage, and a controller connected to the first and second sample circuits. The first and second sample circuits are substantially functionally equivalent to one another but optimized for different regions of operation within a specified range of PVT conditions. The controller is operative to receive respective output signals from the first and second sample circuits, to monitor a functionality of the second sample circuit relative to the first sample circuit, and to adjust a level of the second supply voltage to ensure correct operation of the second sample circuit throughout the specified range of PVT conditions. The digital circuit is operative from the second supply voltage.

Abstract: Electrical devices having tunable capacitance are provided. The tunable capacitance is achieved by placing an appropriate material between substrate layers and by controllably applying a pressure to the material to compress the material or alter the shape of a well in which the material is contained, and thereby alter the capacitance of the electrical device. The composition, shape and dimension of the embedded materials determine how the capacitance of the electrical device is altered upon compression of the embedded material in response to an applied control signal. Generally, as the embedded material is compressed, the material will become more dense and the capacitance of the integrated electrical device is altered.

Abstract: A semiconductor device package comprises a container having a base and side walls of an electrically insulating material. A semiconductor device chip is disposed on the base, and a lead frame extends through the side walls. At least one electrical conductor couples the lead frame to the chip. A first layer of an electrically insulating cured gel covers the chip and the lead frame, and a second layer of an electrically insulating cured gel covers at least the portion of the first layer that covers the chip, but does not extend to the side walls. In one embodiment, the second layer has the shape of a dome. In a preferred embodiment the gel comprises silicone. In another embodiment a third layer of conformal insulating material is disposed on the second layer and essentially fills the container. Also is described is a method of making the package for use with RFLDMOS chips.

Abstract: Various embodiments of the present invention provide systems and methods for reduced latency feedback in a data processing system. For example, some embodiments provide a data processing system that includes a variable gain amplifier, a processing circuit, a data detector, and an error signal calculation circuit. The variable gain amplifier amplifies a data input signal and provides an amplified signal. The processing circuit generates a signal output corresponding to the amplified signal, and includes a conditional multiplication circuit. The conditional multiplication circuit conditionally multiplies the signal output by a gain correction signal and provides the result as an interim output. The data detector applies a data detection algorithm to the signal output and provides an ideal output. The error signal calculation circuit generates a gain correction signal based at least in part on the interim output and a derivative of the ideal output.

Abstract: The invention provides a monolithic, highly integrated power supply circuit capable of providing various voltages for circuits on an expansion card, either from a main supply source or an auxiliary supply source. The monolithic power supply circuit preferably includes two switching converters, two low-drop-out regulators, a standby regulator, a reset circuit, and a control circuit. An associated method for providing various voltages via a monolithic power supply circuit is also disclosed.

Abstract: The invention provides, in one aspect, a semiconductor device that comprises an interconnect layer located over a semiconductor substrate. A passivation layer is located over the interconnect layer and having a solder bump support opening formed therein. Support pillars that comprise a conductive material are located within the solder bump support opening.

Abstract: Various embodiments of the present invention provide systems and methods for storage medium flaw detection. For example, some embodiments provide flaw detection systems that include an input circuit, a data processing circuit and a defect detection circuit. The input circuit is operable to receive an input signal and to provide a filtered output. The data processing circuit is operable to receive the filtered output and to compute a difference between the filtered output and an expected output, and the defect detection circuit receives the difference between the filtered output and the expected output and compares a derivative of the difference with a threshold value, and asserts a defect signal when a magnitude of the derivative of the difference exceeds a threshold value.

Abstract: Certain embodiments of the inventions provide an integrated circuit (IC) having a processor operatively coupled to a PVT (process-voltage-temperature) source and an adjustable memory. The processor receives from the source an input characterizing the present PVT condition and generates a command for the memory based on that input. In response to the command, the memory adjusts its internal circuit structure, clock speed, and/or operating voltage(s) to optimize its performance for the present PVT condition. Advantageously, the ability to adjust the memory so that it can maintain its functionality and deliver an acceptable level of performance under unfavorable PVT conditions provides additional flexibility in choosing circuit design options, which can produce area savings and/or increase the yield of acceptable ICs during manufacture.

Abstract: In described embodiments, elements of a wireless home network employ learned power security for the network. An access point, router, or other wireless base station emits and receives signals having corresponding signal strengths. Wireless devices coupled to the base station through a radio link are moved through the home network at boundary points of the home and the signal strength is measured at each device and communicated to the base station. Based on the signal strength information from the emitted signals measured at the boundary points and/or from measured signal strength information of signals received from the boundary points, the base station determines a network secure area. The base station declines permission of devices attempting to use or join the home network that exhibit signal strength characteristics less than boundary values for the network secure area.

Abstract: A method for scheduling a network resource comprises adding tokens to first and second accumulators at first and second fill rates, respectively. A number of tokens corresponding to a size of a packet is subtracted from the first accumulator and a highest priority is assigned to a queue with which the packet is associated, if a number of tokens in the first accumulator is greater than zero. The number of tokens is subtracted from the second accumulator, and a default priority assigned to the queue, if the number of tokens in the first accumulator is less than zero and a number of tokens in the second accumulator is greater than zero. The network resource is assigned for transmission of the packet from the queue using a schedule that is based on the priority assigned to the queue. The packet is transmitted using the assigned network resource.

Abstract: A unique real time tuning (RTT) process is employed for obtaining the desired optimum device parameter adjustments. The RTT parameter adjustment process is utilized with IP phone or other device chipsets as desired. In one embodiment, RTT provides a graphical user interface to a digital signal processor (DSP), or the like, on the device chipset allowing for observation, evaluation and control of the device parameters in real time. The real time exchange of the device parameter information between the device and an external workstation, e.g., a personal computer or the like, is provided by a User Datagram Protocol (UDP) that runs on a controller on the device, e.g., an ARM processor or the like. In this example, the unique combination of the RTT, UDP and DSP cooperate advantageously to implement, in accordance with the principles of the invention, the desired observability, and control to designers to tune the device, e.g.

Abstract: Methods and apparatus are provided for measuring the performance of a read channel. A number of detection techniques, such as SOVA and maximum-a-posteriori (MAP) detectors, produce a bit decision and a corresponding reliability value associated with the bit decision. The reliability value associated with the bit decision may be expressed, for example, in the form of log likelihood ratios (LLRs). The reliability value can be monitored and used as a performance measure. The present invention provides a channel performance measure that generally correlates directly to the BER but can be collected in less time.

Abstract: Methods and apparatus are provided for communicating data in a multiple antenna communication system having N transmit antennas. According to one aspect of the invention, a header format includes a legacy preamble having at least one legacy long training field and an extended portion having at least N additional long training fields on each of the N transmit antennas, wherein one or more of the at least N additional long training fields are comprised of only one Orthogonal Frequency Division Multiplexing (OFDM) symbol. The extended portion optionally comprises one or more repeated OFDM symbols for frequency offset estimation. In one implementation, the extended portion comprises a first high throughput long training field comprised of two repeated OFDM symbols and N?1 high throughput long training fields comprised of only one OFDM symbol. In another variation, the extended portion comprises N high throughput long training fields comprised of only one OFDM symbol.

Abstract: Methods for fabricating robust films across a patterned underlying layer's edges or steps are disclosed. The novel methods diminish the negative effects of electrode steps or edges on the integrity of a membrane. Thus, the methods are particularly applicable to membrane release technology. The height of the step or edge is eliminated or reduced to increase the mechanical integrity of the film.