Abstract: Various embodiments of the present invention provide systems and methods for media defect detection. For example, a data transfer system is disclosed that includes a data detector, a defect detector and a gating circuit. The data detector provides a soft output, and the defect detector is operable to receive the soft output and the data signal, and to assert a defect indication based at least in part on the soft output and the data signal. The gating circuit is operable to modify the soft output of the detector whenever the defect indication is asserted.

Abstract: Various embodiments of the present invention provide systems and methods for reducing low frequency loss in a magnetic storage device. For example, a data processing circuit is disclosed that includes an amplifier, two filters and a summation element. The amplifier provides an amplified output that is filtered using a first of the two filters to create a first filtered output. The first filtered output is then filtered using the second of the two filters to create a second filtered output. The summation element sums the first filtered output with the second filtered output to provide a pole altered output.

Abstract: The present inventions are related to systems and methods for pre-equalizer noise suppression in a data processing system. As an example, a data processing system is discussed that includes: a sample averaging circuit, a selector circuit, an equalizer circuit, and a mark detector circuit. The sample averaging circuit is operable to average corresponding data samples from at least a first read of a codeword and a second read of the codeword to yield an averaged output based at least in part on a framing signal. The selector circuit is operable to select one of the averaged output and the first read of the codeword as a selected output. The equalizer circuit is operable to equalize the selected output to yield an equalized output, and the mark detector circuit is operable to identify a location mark in the equalized output to yield the framing signal.

Abstract: Various embodiments of the present invention provide systems and methods for data regeneration. For example, a system for regenerating data is disclosed. The system includes a media defect detector that is operable to identify a potential media defect associated with a medium from which an input signal is derived, an attenuation amplitude detector that generates an attenuation factor, and a data detector. The data detector includes a first data path and a second data path. The first data path includes a bank of two or more selectable noise prediction filters and the second data path includes a fixed noise prediction filter and the attenuation factor. The data detector processes a derivative of the input signal using the second data path when the potential media defect is indicated, and processes the derivative of the input signal using the first data path when a media defect is not indicated.

Abstract: An improved speakerphone for a cellular telephone, portable telephone handset, or the like. In one embodiment, a receiver provides an audio signal, and a first phase-shifter phase-shifts the audio signal by a first phase-shift amount. A second phase-shifter phase-shifts the audio signal by a second phase-shift amount and drives a loudspeaker. A detector generates average and peak values of the first phase-shifted audio signal. A processor sets the first phase-shift amount to each one of a plurality of phase-shift amounts and calculates a corresponding average-to-peak ratio value from the peak and average values. The processor then selects one of the plurality of phase-shift amounts having a corresponding average-to-peak ratio value that meets at least one criteria (e.g., the largest one of the average-to-peak ratio values), and then sets the second phase-shift amount to be the same as the selected phase-shift amount. This enhances the perceived loudness of sound from loudspeaker.

Abstract: A memory device comprises a memory array and error correction circuitry coupled to the memory array. The error correction circuitry is configured to identify, in a data word retrieved from the memory array, at least one bit position corresponding to a predetermined defect location in the memory array, and to generate a corrected data word by automatically inverting a logic value at the identified bit position. This automatic logic inversion approach is particularly well suited for use in correcting output data errors associated with via defects and weak bit defects in high-density ROM devices.

Abstract: Most recently accessed frames are locked in a cache memory. The most recently accessed frames are likely to be accessed by a task again in the near future and may be locked at the beginning of a task switch or interrupt to improve cache performance. The list of most recently used frames is updated as a task executes and may be embodied as a list of frame addresses or a flag associated with each frame. The list of most recently used frames may be separately maintained for each task if multiple tasks may interrupt each other. An adaptive frame unlocking mechanism is also disclosed that automatically unlocks frames that may cause a significant performance degradation for a task. The adaptive frame unlocking mechanism monitors a number of times a task experiences a frame miss and unlocks a given frame if the number of frame misses exceeds a predefined threshold.

Abstract: A cellular device has a stacked protocol, with an upper layer and a lower layer. The lower layer includes a multiple carrier detection unit, a memory and a digital processing system. The multiple carrier detection unit receives a plurality of wireless carrier signals and provides a respective plurality of output digital streams. The memory is used to store a target cell search list, and the digital processing system processes the digital streams in parallel based upon parameters within the target cell search list. The parameters may include a frequency indicator and a radio access technology (RAT) indicator. The lower layer controls the multiple carrier detection unit to detect the wireless carrier signals based upon the frequencies and RATs in the target cell search list.

Abstract: Methods and apparatus are provided for N+1 packet level mesh protection. An error correction encoder is provided for encoding message symbols, m0 through mN?1, to generate a codeword that includes the message symbols, m0 through mN?1, and one or more check symbols. The error correction encoder comprises a linear feedback shift register having one or more flip-flops to generate the check symbols after shifting the message symbols, m0 through mN?1, through the linear feedback shift register. An error correction decoder is also provided for decoding a codeword that includes message symbols, m0 through mN?1, and one or more check symbols. The error correction decoder comprises a linear feedback shift register having one or more flip-flops to generate an error symbol based on a remainder after shifting the message symbols, m0 through mN?1, and the one or more check symbols through the linear feedback shift register.

Abstract: A path comparison unit is disclosed for determining paths in a trellis that compete with a survivor path. The disclosed path comparison unit comprises a first type functional unit comprising a multiplexer and a register to store one or more survivor bits associated with the survivor path; and at least two second type functional units, wherein each second type functional unit comprises a multiplexer and a logical circuit to compute at least one equivalence bit indicating whether the bit for a respective path and the bit for the survivor path are equivalent. Generally, the respective path is one or more of a win-lose path and a lose-win path.

Abstract: Methods and apparatus are provided for adaptive link partner transmitter equalization. According to one aspect of the invention, a local transceiver adapts one or more equalization parameters of a link partner by receiving a training frame over a channel between the link partner and the local transceiver, wherein the training frame is comprised of a predefined training pattern; adjusting one or more of the equalization parameters of the link partner; and determining whether the equalization of the channel satisfies one or more predefined criteria based on whether the predefined training pattern is properly received by the local transceiver. The predefined training pattern can be a pseudo random pattern, such as a PN11 pattern Noise margins and jitters margins for the channel can optionally be improved.

Abstract: Methods and apparatus are provided for equalizing a received signal. A received signal is equalized by determining a data rate of the received signal; obtaining one or more equalization parameters associated with the determined data rate; and equalizing the received signal using the obtained one or more equalization parameters. The equalization parameters may comprise, for example, one or more of a gain parameter, zero control for a high pass filter and one or more threshold settings for one or more latches used during the equalizing step, such as data latches or transition latches (or both).

Abstract: A method and apparatus are provided for wireless communication between an integrated circuit device and a monitoring station. Each integrated circuit device has one or more antennas that permit wireless communication with an external monitoring station. A signal destined for an integrated circuit device is transmitted by the monitoring station using an associated antenna. An antenna associated with the destination integrated circuit receives the transmitted signal. The antenna(s) may be embodied, for example, as pins that are external to the integrated circuit device, or printed or etched on the integrated circuit device itself. Greater bandwidth can be achieved, if necessary, by pooling the bandwidth of several antennas.

Abstract: An IO interface circuit for use in a high voltage tolerant application is provided. The IO interface circuit includes a signal pad and at least a first parasitic bipolar transistor having an emitter adapted for connection to a voltage return of the interface circuit, a base adapted to receive a first control signal, and a collector connected directly to the signal pad in an open collector configuration. The interface circuit further includes a MOS control circuit coupled to the parasitic bipolar transistor and being operative to generate the first control signal. The IO interface circuit may further include an active pull-up circuit connected between a voltage supply of the interface circuit and the signal pad.

Abstract: A technique for estimating the Doppler frequency of an input signal comprising a pilot signal. In one embodiment, the technique comprises: (a) accumulating a plurality of samples from the input signal over a specified time duration to derive a channel tap estimate; (b) obtaining a sequence of channel tap estimates by repeating step (a) until a specified number of channel tap estimates have been accumulated; (c) performing a Fourier transform of the sequence of channel tap estimates to obtain a complex sequence of values; (d) finding the smallest index value for which a power spectral distribution function of the complex sequence of values exceeds a specified threshold; and (e) obtaining an estimate of the Doppler frequency by dividing the smallest index value found in step (d) by the product of the specified number of channel tap estimates and the specified time duration.

Abstract: In one embodiment of the present invention, the performance of an electronic circuit having a clock path between a clock source cell and a clock leaf cell is characterized over a simulation duration, where the clock path has one or more intermediate cells. Variations in the effective power supply voltage level of at least one intermediate cell over the simulation duration are determined using a system-level power-grid simulation tool. Static timing analysis (STA) software is used to determine cell delays for at least one of the intermediate cells for different clock-signal transitions at different times during the simulation duration. The cell delays are then used to generate one or more metrics characterizing the performance of the electronic circuit, such as maximum and minimum pulse widths, maximum cycle-to-cycle jitter, and maximum periodic jitter.

Abstract: Various data acquisition, storage and/or distribution systems and devices are described herein. As one example, a mobile data acquisition and distribution device is described. The device includes a non-volatile storage medium, a wireless interface, and a processor. The non-volatile storage medium includes instructions executable by the processor to: receive a user data set, and to store the user data set to the non-volatile storage medium. The instructions are further executable by the processor to receive a request initiated through a remote user interface via the wireless interface. Where the request is to provide the user data set to a recipient device, the instructions are further executable by the processor to provide the user data set to the recipient device via the wireless interface.

Abstract: Various systems and methods for power management are disclosed herein. For example, a modular, adaptive power management system for use in a hard disk drive system is disclosed. This modular, adaptive power management system includes a hard disk drive controller, a read channel module, a host interface controller and a power manager system. The hard disk controller includes a processor executing firmware, and the host interface controller provides for host access via a host interface. The host interface may be, for example, an ATA interface, a SATA interface, and/or other emerging serial interfaces such as MMC, CE-ATA or SDIO. The power manager system includes a power island register and an oscillation control register. Both the power island register and the oscillation control register are each at least indirectly writable via the firmware and via the host interface.

Abstract: A short range radio transmitter device includes a radio signal modulator and transmitter, a receiver and a controller coupled to the receiver. The controller and receiver operate to examine a frequency spectrum to select a transmission frequency for the radio signal modulator and transmitter. A receiver system for use with the transmitter includes a data channel service enabled receiver and a controller. The controller of the receiver system automatically tunes the data channel service enabled receiver to a frequency identified in a data channel service component of a received signal.

Abstract: In one embodiment, a method for demodulating and searching for a preamble signal containing a complex phasor signal is disclosed. The complex phasor is demodulated using a phasor-rotated fast transformer. A received signal is correlated with a spreading code to produce a correlated signal. The correlated signal is coherently accumulated to produce a coherently accumulated signal. A first phasor-rotated signal transformation is performed on a real component of the coherently accumulated signal, and a second phasor-rotated signal transformation is performed on an imaginary component of the coherently accumulated signal. Finally, the signal power of the transformed real and imaginary components of the coherently accumulated signal is determined.