Abstract: Various embodiments of the present invention provide systems and methods for sector address mark detection. As an example, data detection systems are disclosed that include a sector address mark detection circuit and a sector address mark quality detection circuit. The sector address mark detection circuit receives a data stream and identifies a sector address mark in the data stream. The sector address mark quality detection circuit receives a first sample and a second sample from the data stream corresponding to the sector address mark, and determines a quality of the sector address mark based at least in part on the first sample and the second sample. In various cases, one or more of the samples of the sector address mark up to all of the samples of the sector address mark may be used.

Abstract: A portable electronic device is operative to facilitate power sharing with at least a second electronic device coupled thereto. The portable electronic device includes a battery power source, a first port adapted for connection to a first network connection and a second port adapted for connection to a second network connection. An input stage in the portable electronic device is connected to the first port. The input stage is operative to supply power received from the first network connection through the first port to the battery power source for recharging the battery power source. The portable electronic device further includes an output stage connected to the second port. The output stage is operative to supply power from the battery power source to the second network connection through the second port.

Abstract: Various systems and methods for power management are disclosed herein. For example, a synchronous semiconductor circuit is disclosed that includes two or more clock sources and a power management controller. The power management controller is operable to apply power to one of the clock sources and to select another of the clock sources for synchronization of the circuit. Then, upon stabilization of the first clock source, it is selected by the power management controller to synchronize the circuit.

Abstract: In serial communications, jitter is an unwanted variation of one or more signal characteristics. Two-dimensional modulation circuits and methods incorporate an amplitude pre-emphasis scheme as well as a transmit duty cycle pre-distortion (pre-DCD) technique to reduce jitter. The pre-DCD technique directly addresses transition edges of the data signal and is combined with amplitude pre-emphasis to improved data transmission.

Abstract: In one embodiment, C input audio channels are encoded to generate E transmitted audio channel(s), where one or more cue codes are generated for two or more of the C input channels, and the C input channels are downmixed to generate the E transmitted channel(s), where C>E?1. One or more of the C input channels and the E transmitted channel(s) are analyzed to generate a flag indicating whether or not a decoder of the E transmitted channel(s) should perform envelope shaping during decoding of the E transmitted channel(s). In one implementation, envelope shaping adjusts a temporal envelope of a decoded channel generated by the decoder to substantially match a temporal envelope of a corresponding transmitted channel.

Abstract: The invention provides a communication protocol and serial interface having an approximately fixed interface clock and capable of accommodating a variety of communication rates. The interface employs a variable-length frame that may be expanded or reduced to obtain a desired communication rate, even though the interface clock rate is held approximately constant. The invention further provides a method for designing an agile barrier interface. In particular, the barrier clock rate is preferably selected to be an approximate common multiple of the various communication rates that the barrier interface must handle. The frame length corresponding to each communication rate may then be obtained by dividing the barrier clock rate by the EA rate. Finally, the invention provides an agile barrier capable of communicating data across a serial interface at a variety of data rates and at an approximately fixed interface clock rate.

Abstract: A survivor path memory is provided for a Viterbi detector. The survivor path memory comprises a plurality of columns, each associated with a different time step, and an input processor. Each column comprises a flip flop for storing one bit or portion of a bit sequence associated with a Viterbi state; and a multiplexer for each state controlled by a case signal indicating a time step, the multiplexer selecting a state from a previous time step, wherein an output of the multiplexer of a given state is connected to at least one data input of a flip flop of the given state. The input processor generates a control signal that exchanges one or more pointers based on a trellis structure, wherein each of the pointers points to one of the flip flops.

Abstract: A representative digital circuit of the invention has an on-chip, non-volatile memory, to which chip-specific speed-binning data that characterize performance of the digital circuit are written during production testing. During normal operation, the power controller that controls power-supply signals applied to the digital circuit reads the speed-binning data from the on-chip memory for use as input parameters for dynamic supply-voltage scaling, dynamic clock scaling, and/or adaptive power control that optimize (e.g., minimize) power consumption in the digital circuit. Advantageously over the prior art, the accuracy and efficiency of dynamic and/or adaptive power control arc improved because the chip-specific speed-binning data enable the power controller to better customize the power-management algorithm for the given digital circuit.

Abstract: Various systems and methods for reducing cross coupling in proximate signals are disclosed. As one example, a system for reducing cross-coupling in adjacent signals that includes an active slew rate limiter circuit is disclosed. The active slew rate limiter circuit is operable to receive an input signal, and to provide an output signal based on the input signal with a controlled slew rate. In some cases, such systems may be included within a storage device that includes a read head. In such cases, the systems may operate to assure a substantially constant power dissipation within the read head.

Abstract: A scheduler is adapted to schedule packets or other data blocks for transmission from a plurality of transmission elements in timeslots of a frame in a communication system. In scheduling for a given frame, the scheduler initially designates each of the transmission elements as eligible to transmit one or more data blocks in the given frame, and selects from among those of the transmission elements designated as eligible at least one of the transmission elements for scheduling in a next available timeslot of the given frame. The scheduler then adjusts the eligibility status of the selected transmission element(s), and repeats the selecting and adjusting operations for one or more remaining timeslots of the given frame. The scheduler in an illustrative embodiment may be implemented in a network processor integrated circuit or other processing device of the communication system.

Abstract: Forming a thin film acoustic device by patterning a layer of non-conducting material on a first side of a substrate to expose a portion of the first substrate side; depositing layers of conducting material on the layer of non-conducting material and the exposed portion of the first substrate side; depositing a layer of piezoelectric material on the layers of conducting material; depositing and patterning additional layers of material on the layer of piezoelectric material to form a first device electrode; depositing and patterning a masking layer on a second side of the substrate to expose a portion of the second substrate side; etching away the exposed substrate portion to expose the patterned layer of non-conducting material and a portion of the layers of conducting material; and etching away the exposed portion of the layers of conducting material to form a second device electrode.

Abstract: A method for forming a germanium-enriched region in a heterojunction bipolar transistor and a heterojunction bipolar transistor comprising a germanium-enriched region. A base having a silicon-germanium portion is formed over a collector. Thermal oxidation of the base causes a germanium-enriched region to form on a surface of the silicon-germanium portion subjected to the thermal oxidation. An emitter is formed overlying the germanium-enriched portion region. The germanium-enriched region imparts advantageous operating properties to the heterojunction bipolar transistor, including improved high-frequency/high-speed operation.

Abstract: In one embodiment, a method for demodulating and searching for a preamble signal containing a complex phasor signal is disclosed. The complex phasor is demodulated using a phasor-rotated fast transformer. A received signal is correlated with a spreading code to produce a correlated signal. The correlated signal is coherently accumulated to produce a coherently accumulated signal. A first phasor-rotated signal transformation is performed on a real component of the coherently accumulated signal, and a second phasor-rotated signal transformation is performed on an imaginary component of the coherently accumulated signal. Finally, the signal power of the transformed real and imaginary components of the coherently accumulated signal is determined.

Abstract: A QFN IC package is provided that has all of the advantages of the typical QFN IC package, but in addition, has a paddle that is configured to facilitate trace routing and/or via placement on the PWB or PCB on which the IC package is mounted. By configuring the paddle as necessary or desired in order to facilitate routing and/or via placement, the overall size of the PWB or PCB can be reduced without sacrificing the thermal or electrical performance advantages that the paddle provides. In addition, the reduction in the overall size of the PWB or PCB results in reduced cost.

Abstract: A method and apparatus are provided for determining a plurality of filter tap weights or biases (or both) for a noise predictive filter used to generate one or more signal dependent branch metrics. A filter tap weight or filter bias (or both) are adaptively accumulated for each possible data condition. The data conditions may comprise, for example, each possible data pattern for a given data dependency length. The appropriate accumulated filter tap weight or bias to update can be selected based on a data condition associated with the current received data. The filter tap weights associated with a delay 0 tap can be adapted for each filter condition except for a single normalizing condition, whose corresponding delay 0 tap remains fixed.

Abstract: Methods and apparatus are provided for improved startup of a voltage controlled delay loop that has an injection clock and a return clock. A control signal is determined for a plurality of delay elements in a voltage controlled delay loop by obtaining a histogram count of a number of occurrences of at least one predefined logic value for a plurality of delay settings of the voltage controlled delay loop; determining a histogram count that approximately corresponds to an alignment of at least one edge in the injection and return clocks; and determining the control signal based on the determined histogram count that approximately corresponds to the alignment. The voltage controlled delay loop can be started using the determined control signal. The histogram count can be obtained for a plurality of PVT combinations and the control signal can then be determined for each PVT combination.

Abstract: Petri net models, of systems, communication protocols, and software programs, which include place objects, transition objects, arcs, and initial markings, may be used for testing and verification. To reduce computations, a new unfolding process is performed on the net models. Two or more candidate buffer place interfaces are selected from the input net model. The input net is subdivided with a preliminary cut to form two subnets, wherein the preliminary cut passes through suitable candidate buffer place interfaces, objects of each of the subnets other than the suitable candidate buffer place interfaces are reachable from at least one initial marking, and the subnets do not include a mix of initial and non-initial marking places. Each of the two subnets are unfolded and then joined to form an unfolded net that is behaviorally equivalent to original input net model. The unfolded net is then stored in a storage unit.

Abstract: Described embodiments provide a server for transferring data packets of streaming data sessions between devices. The server includes an accelerator that, for received data packets, i) extracts header fields of the packets, ii) determines, based on the header fields, a destination for the packets, and iii) provides the packets to the destination. For data to be transmitted, the accelerator i) groups the data into packets, ii) generates header fields for the packets, and iii) provides the packets to the network. A memory arbiter manages accesses to memory that buffers data and stores keys corresponding to the data sessions. A storage medium stores media files corresponding to the data sessions. A key manager includes i) a first memory for storing a master key of the server, ii) a second memory for storing one or more keys corresponding to the data sessions, and iii) a processor to encrypt and decrypt data.

Abstract: Various embodiments of the present invention provide systems and methods for detecting storage medium defects. As one example, a media defect detection system is disclosed that includes a data detector circuit that applies a detection algorithm to the data input and provides a hard output and a soft output. A first circuit combines a first derivative of the hard output with a derivative of the data input to yield a first combined signal. A second circuit combines a second derivative of the hard output with a derivative of the first combined signal to yield a second combined signal. A third circuit combines a derivative of the soft output with the second combined signal and a threshold value to yield a defect signal.

Abstract: In a packet-based (e.g., Ethernet) network, such as the network of central offices and base stations of a wireless telephone system, a node receives one or more incoming packet-based signals from one or more other nodes of the network and recovers a clock signal from each incoming packet-based signal. The node selects one of the recovered clock signals as the node's reference clock signal. When the node is part of a base station, the node uses the selected clock to generate and transmit one or more outgoing packet-based signals to one or more central offices. The node also uses the selected clock to generate the base station's wireless transmissions. In one implementation, the base stations and central offices are connected by Ethernet facilities.