Abstract: Methods and apparatus are provided for determining receiver filter coefficients for a plurality of phases. One or more coefficients for a receiver filter are determined by determining a first coefficient for a first phase of a data eye; and determining a second coefficient for a second phase of the data eye. The receiver filter may be, for example, a decision-feedback equalizer. The first and second coefficients may be determined by performing an LMS adaptation of decision-feedback equalization coefficients. In another embodiment, the first and second coefficients may be determined by obtaining eye opening metrics from a data eye monitor corresponding to each of the respective first phase and the second phase; and determining the respective first and second coefficients based on the eye opening metrics. The first and second phases can correspond to odd and even phases.

Abstract: The invention, in one aspect, provides a semiconductor device that comprises a collector located in a semiconductor substrate and an isolation region located under the collector, wherein a peak dopant concentration of the isolation region is separated from a peak dopant concentration of the collector that ranges from about 0.9 microns to about 2.0 microns.

Abstract: In one embodiment, a demapper uses two hybrid-QPSK constellations to demap pairs of equalized data symbols recovered from 16-QAM, DCM OFDM symbols, wherein the equalized data symbols in a pair correspond to the same four-bit group. A first hybrid-QPSK constellation is generated by combining the real components of both 16-QAM mapping constellations onto one coordinate plane. The demapper generates a first set of two decision variables by combining the real components of each equalized data symbol in a pair to correspond to the first hybrid-QPSK coordinate plane. A log-likelihood ratio is then calculated for both decision variables in the set to determine likelihood estimates for the first and second bits of the four-bit group. This process is repeated for the imaginary components of each corresponding pair of equalized data symbols to generate likelihood estimates for the third and fourth bits of the four-bit group.

Abstract: In one embodiment, a receiver has a reference generator and a main equalizer. The reference generator equalizes a received signal using one or more pilot reference signals. Then, the reference generator decodes one or more predetermined data channels of the equalized signal, makes hard decisions on the data of each decoded channel, and regenerates the original coding sequence of each decoded channel. The main equalizer uses each re-encoded channel as an additional reference signal along with one or more pilot signals to equalize a time-delayed version of the received signal. In alternative embodiments, the receiver might also have a step-size generator which selects optimum step sizes from a look-up table based on the number of re-encoded channels and the power of those channels. The step size is then used by the main equalizer along with the re-encoded channels to equalize the time-delayed received signal.

Abstract: Various embodiments of the present invention provide systems and methods for determining fly height. For example, a system for fly height determination is disclosed that includes a head assembly disposed in relation to a storage medium, a write channel, and a read circuit. The read circuit is operable to receive information from both the head assembly and the write channel. A frequency determination circuit is included that is operable to receive a first signal from the read circuit corresponding to information received from the write channel and to provide a first fundamental frequency and a first higher order frequency based on the first signal, and the frequency determination circuit is operable to receive a second signal from the read circuit corresponding to information received from the head assembly channel and to provide a second fundamental frequency and a second higher order frequency based on the second signal.

Abstract: An electronically steerable antenna includes at least one driven element, at least one controllable counterpoise element, and a support structure on which the driven element and the controllable counterpoise element are disposed. The controllable counterpoise element has at least one geometric characteristic which can be varied. A radiating angle of the driven element is selectively controlled, at least in part, by modifying the geometric characteristic of the at least one controllable counterpoise element. The counterpoise element may include multiple conductive segments, at least a subset of which may be adapted to be individually electrically connected together so as to modify the radiating angle of the driven, element.

Abstract: Various embodiments of the present invention provide systems and methods for data regeneration. For example, a system for data regeneration is disclosed that includes a data input derived from the medium. A data detector and a data recovery system receive the data input. The data detector provides a first soft output, and the data recovery system provides a second soft output. The first soft output and the second soft output are provided to a multiplexer. A media defect detector performs a media defect detection process, and provides a defect flag that indicates whether the data input is derived form a defective portion of the medium. The defect flag is provided to the multiplexer where it is used to select whether the first soft output or the second soft output is provides as an extrinsic output.

Abstract: A packet delay variation simulation system has a packet generator, a packet delay variation generator, and a packet delay analyzer to analyze delayed packets. The packet delay variation generator has multiple delay distribution modules that use both a deterministic delay process and a statistical delay process packet for determining a packet's delay. The packet delay variation generator may utilize different probability density functions to describe various portions of measured packet data. That is, measured packet delay information is analyzed and information from this analysis is used to construct a total delay model for a network. The delay may include a pre-determined deterministic delay offset as well as one or more variable statistical delay offsets.

Abstract: A method and apparatus are disclosed for performing joint equalization and decoding of multidimensional codes transmitted over multiple symbol durations. An RSSE scheme is disclosed that cancels the intrasymbol interference caused by other symbol components within the same multidimensional code symbol. The disclosed RSSE technique for multidimensional codes applies where the number of trellis code dimensions exceeds the number of channels. The disclosed RSSE decoder computes the intersymbol interference caused by previously decoded multidimensional code symbols. In addition, a branch metrics unit compensates for the intrasymbol interference caused by other symbol components within the same multidimensional code symbol. In addition, the disclosed RSSE decoder compensates for the intrasymbol interference caused by other symbol components within the same multidimensional code symbol.

Abstract: Methods and systems are provided for transmitting a plurality of information signals in a multiple antenna communication system. One or more information signals are coded using a plurality of coders to generate the plurality of coded information signals and an Inverse Fast Fourier Transformation is performed on each of the plurality of coded information signals to create a corresponding output signal. Each of the corresponding output signals are transmitted on a different antenna. Each of the plurality of coded information signals can optionally be separated into K signals, On the receiver side, a signal comprising K different frequencies is received on at least N receive antennas and a Fast Fourier Transformation is applied to each of the at least N received versions of the signal comprising K different frequencies to generate N*K low frequency signals.

Abstract: The invention is a virtual gateway that mediates between a dual-mode subscriber device and an IP-based PBX. In particular, the virtual gateway includes a WLAN interface for communicating with the dual-mode subscriber device and a network interface (wired or wireless) for communicating with the IP-based PBX over the Internet. As such, the virtual gateway may relay voice and call control instructions between the dual-mode subscriber device and the IP-based PBX, and may provide the same call control functions to the dual-mode subscriber device provided by the call control processor in existing dual-mode phones. The invention further provides a dual-mode subscriber device suitable for operation with the virtual gateway. Because the dual-mode subscriber device does not require a call control processor, the battery life and cost of the device are significantly improved.

Abstract: An ESD protection circuit includes a first voltage clamp, connected between a first voltage supply node and a second voltage supply node of the circuit, and a second voltage clamp, connected between the second voltage supply node and a voltage return of the circuit. The first voltage supply node is adapted to receive a first voltage which is greater than a prescribed gate oxide reliability potential of the circuit. The second voltage supply node is operative to receive a second voltage which is less than the first voltage. The first voltage clamp is operative to clamp the first voltage on the first voltage supply node to a first value during an ESD event between the first and second voltage supply nodes, and the second voltage clamp is operative to clamp the second voltage on the second voltage supply node to a second value during an ESD event between the second voltage supply node and the voltage return.

Abstract: The present invention, in one aspect, provides an integrated circuit that comprises a first region of transistors having gate structures with a low dopant concentration, and a second region of transistors having gate structures with a dopant concentration substantially higher than the gate structures of the first region, and wherein the transistors in the first region comprise a substantial portion of the integrated circuit. The transistors may include a resistor region located between an upper portion of the gate and the gate dielectric.

Abstract: According to one embodiment, during mixing of an N-channel input signal to generate an M-channel output signal, in at least one frequency sub-band, magnitude equalization is applied to the mixed channel signals such that an amplitude sum magnitude for the N input channels (e.g., the magnitude of a sum of estimated amplitudes of the N input channels) is approximately equal to an amplitude sum magnitude for the M output channels (e.g., the magnitude of a sum of estimated amplitudes of the M output channels). In one implementation, magnitude equalization is applied to one or more sub-bands (e.g., those below 1 kHz), and power equalization is applied to one or more other sub-bands (e.g., those above 1 kHz) to reduce coloration effects in the output signal.

Abstract: A method and apparatus are disclosed for detecting a collision in a carrier sense multiple access wireless communication system. Each transmitting station includes a collision detector that evaluates one or more predefined criteria to determine when a collision has occurred. The collision detector evaluates the measured energy level and optionally payload and/or preamble detection information to determine if a collision has occurred. A collision occurred when an expected ACK message is not received, in the presence of an increased energy level and possibly preamble or payload detection information. The collision detector of the present invention can be activated, for example, at a time corresponding to the start of the 802.11 Short Inter Frame Space interval.

Abstract: One embodiment of the present invention processes a signal of interest through an optional reference channel, combines the resulting signal with white noise, and then processes the noisy signal through a reference receiver. Two metrics are calculated from the results of that processing: Non-Compensable Data-Dependent Jitter (NC-DDJ) and Enhanced Transmitter and Waveform Dispersion Penalty (Enhanced TWDP). Within the reference receiver, a variable delay module sweeps the eye opening defined by the noise-free samples of the signal of interest and determines the transition points (i.e., edges) of the eye opening. Those transition points are compared to the Unit Interval to yield NC-DDJ. Further, the signal-to-noise ratio (SNR) of the noisy samples of the signal of interest is compared to the SNR of an ideal receiver (i.e., matched filter) driven by an ideal transmitter via an ideal channel with additive white Gaussian noise n(t) to yield Enhanced TWDP.

Abstract: A method for forming BiCMOS integrated circuits and structures formed according to the method. After forming doped wells and gate stacks for the CMOS devices and collector and base regions for the bipolar junction transistor, an emitter layer is formed within an emitter window. A dielectric material layer is formed over the emitter layer and remains in place during etching of the emitter layer and removal of the etch mask. The dielectric material layer further remains in place during source/drain implant doping and activation of the implanted source/drain dopants. The dielectric material layer functions as a thermal barrier, to limit out-diffusion of the emitter dopants during the activation step.

Abstract: Asynchronous/plesiochronous digital hierarchy (PDH) signals, such as DS1 and E1, are transported using virtual concatenation. The packetized data signals are frame encapsulated and subsequently inverse multiplexed into a plurality of PDH frames. An overhead packet is inserted in the transmitted frames to enable the receiver to determine the status of the frames and extract the differential delay experienced by various frames as they are routed through virtually concatenated channels. The extracted delays enables the receiver to realign the various frames of the PDH signal to reconstitute the originally transmitted signals that travel through different paths of the transport network linking the source and sink of the virtually concatenated channel.

Abstract: In accordance with described exemplary embodiments, correction is inserted into the feedback loop of a second order resonator used at the time of frequency transition. The correction is based upon parameters generated from a desired output signal frequency and a desired sampling frequency. The correction is generated to maintain i) constant amplitude, ii) continuous phase, and iii) the same sampling frequency during the frequency transition.

Abstract: One aspect provides a method of standardized data creation and analysis of semiconductor technology node characteristics. In one embodiment, the method includes: (1) designing representative benchmark circuits for a clock path, a data path and a flip-flop path, (2) establishing at least one standard sensitization and measurement rule for delay and power for the representative benchmark circuits and across corners in the technology nodes, (3) performing a simulation by sweeping through a range of values and at predetermined intervals across the corners, (4) extracting data from the simulation, (5) writing the data to a databank and (6) parsing and interpreting the data to produce at least one report.