Abstract: Methods and apparatus are provided for measuring the performance of a read channel. A number of detection techniques, such as SOVA and maximum-a-posteriori (MAP) detectors, produce a bit decision and a corresponding reliability value associated with the bit decision. The reliability value associated with the bit decision may be expressed, for example, in the form of log likelihood ratios (LLRs). The reliability value can be monitored and used as a performance measure. The present invention provides a channel performance measure that generally correlates directly to the BER but can be collected in less time.

Abstract: Various apparatuses and methods for offsetting the phase and/or frequency of a clock signal are disclosed herein. For example, some embodiments provide an apparatus for generating a clock signal, including a quadrature delay circuit connected to an input clock signal. The quadrature delay circuit outputs components of the input clock signal with different phase shifts. A first amplitude modulator is connected to the first output of the quadrature delay circuit, and a second amplitude modulator is connected to the second output of the quadrature delay circuit. A summer combines the output of the first and second amplitude modulators.

Abstract: The specification describes matched capacitor pairs that employ interconnect metal in an interdigitated form, and are made with an area efficient configuration. In addition, structural variations between capacitors in the capacitor pair are minimized to provide optimum matching. According to the invention, the capacitor pairs are interdigitated in a manner that ensures that the plates of each pair occupy common area on the substrate. Structural anomalies due to process conditions are compensated in that a given anomaly affects both capacitors in the same way. Two of the capacitor plates, one in each pair, are formed of comb structures, with the fingers of the combs interdigitated. The other plates are formed using one or more plates interleaved between the interdigitated plates.

Abstract: Methods and apparatus are provided for improving the jitter tolerance in an SFP limit amplified signal. Jitter tolerance is improved in a communications receiver by applying a received signal to an SFP limiting amplifier; and applying an output of the SFP limiting amplifier to a low pass filter to improve the jitter tolerance. The low pass filter optionally applies a programmable amount of attenuation to high frequency components of the output. The low pass filter slew rate controls (i.e., rotates) a data eye representation of the received signal to increase the data eye representation along a time axis. The noise margin of the received signal can optionally be improved by applying an output of the low pass filter to an all pass filter. A slew rate controller can evaluate the data eye statistics to determine a setting for the low pass filter.

Abstract: Methods and systems are provided for transmitting a plurality of information signals in a multiple antenna communication system. One or more information signals are coded using a plurality of coders to generate the plurality of coded information signals and an Inverse Fast Fourier Transformation is performed on each of the plurality of coded information signals to create a corresponding output signal. Each of the corresponding output signals are transmitted on a different antenna. Each of the plurality of coded information signals can optionally be separated into K signals. On the receiver side, a signal comprising K different frequencies is received on at least N receive antennas and a Fast Fourier Transformation is applied to each of the at least N received versions of the signal comprising K different frequencies to generate N*K low frequency signals.

Abstract: Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. In another aspect, warping of an integrated circuit device comprising at least one die attached to a base is controlled by applying a counterbalancing layer to at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die.

Abstract: A method for designing a read-only memory (ROM), and related device, includes partitioning a dataset into two or more sub-datasets that each have the same address space, but are of a smaller bit-width than the original dataset. The sub-datasets are row collapsed, and then respective memory cells for the sub-datasets are provided. The output of the memory cells provides the output of the ROM. Each memory cell includes a decoder that maps addresses to word lines based on mapping information obtained during row collapsing, and a logic array driven by the decoder that encodes the data words of the sub-dataset.

Abstract: A pipelined decision feedback unit (DFU) is disclosed for use in reduced-state Viterbi detectors with local feedback. The disclosed pipelined decision feedback unit improves the maximum data rate that may be achieved by the reduced state Viterbi detector by the pipelined computation of partial intersymbol interference-based estimates. A pipelined decision feedback unit is thus disclosed that computes a plurality of partial intersymbol interference based estimates, wherein at least one partial intersymbol interference-based estimate is based on a selected partial intersymbol interference-based estimate; and selects the selected partial intersymbol interference-based estimate from among partial intersymbol interference-based estimates for path extensions into a state.

Abstract: A network processor for determining one or more network operations to be performed on a packet of data in a network comprises processing circuitry and protocol indicator circuitry. The packet of data contains information populating a plurality of protocol header fields. Moreover, the protocol indicator circuitry comprises a plurality of memory elements, each memory element associated with a protocol header field in the plurality of protocol header fields. The processing circuitry determines the one or more network operations to be performed on the packet of data at least in part by addressing one or more lookup tables with the contents of a subset of the plurality of protocol header fields in the packet. This subset is determined by reference to the memory elements in the protocol indicator circuitry. Each memory element is capable of being programmed to indicate whether the associated protocol header field is to be utilized by the processing circuitry in addressing the one or more lookup tables.

Abstract: A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. A variety of silicided and non-silicided) structures may be formed.

Abstract: Several system diagnostic and network management tools are disclosed that, as a primary goal, support the consumer's ability to self diagnose and solve an existing problem. A non-intrusive diagnostic tool is provided that exposes system parameters of a consumer system for remote analysis by qualified personnel. Important data parameters of a given radio receiver are preferably predetermined and gathered directly at the receiver. Then, they are uploaded via the Internet from a removable memory placed into an Internet terminal (e.g., PC), or through a temporary docking station connected to an Internet terminal. This leads toward quick and efficient problem resolution with a properly informed customer service representative that is crucial to enriching the consumer's experience. The data collected relating to relevant system parameters may be used by service providers to enhance or even in some cases enable services.

Abstract: Methods and apparatus are provided for storing survivor paths in a Viterbi detector. At least one register and at least one pointer are maintained for each state. Each register stores a bit sequence associated with a Viterbi state and each pointer points to one of the registers. A trellis transition type is determined, for example, based on a decision from an add/compare/select unit. One or more predefined rules based on a trellis structure and the trellis transition type are employed to exchange one or more of the pointers and to update one or more of the at least one registers. A survivor path memory is also disclosed for a Viterbi detector. The survivor path memory comprises a plurality of columns, each associated with a different time step, and an input processor. Each column comprises a latch for storing one bit of a bit sequence associated with a Viterbi state.

Abstract: A wireless receiver detects signals received at two or more antennas, with each antenna coupled to an input receive chain. A switch is employed to couple selected input receive chains to one or more corresponding output receive chains during listening, coarse-detection, and fine-adjustment modes. At least one channel selection filter (CSF) is employed in each output receive chain, and the receiver employs sub-ranging. During idle mode, one antenna's input receive chain is connected to two or more CSFs to detect the packet. When the packet is detected, during a coarse-adjustment mode, the CSFs are reconfigured to couple each antenna's input receive chain to a corresponding output receive chain using low-gain signals. During fine-adjustment mode, the various gains are adjusted to be either high- or low-gain to maintain signals within the dynamic range of the corresponding CSFs.

Abstract: Techniques for ball bonding wires in an integrated circuit are provided which allow formation of desired wire bond profile shapes for optimal performance. A wire is ball bonded to a first bond site in the integrated circuit with a bonding tool and at least one bend is formed in the wire. The wire is terminated at a second bond site with the bonding tool, thereby creating a wire bond profile. The technique is repeated for a plurality of additional wire bonds of the integrated circuit, and at least two wire bond profiles in the integrated circuit are substantially perpendicular to one another at a crossing point of the profiles.

Abstract: In an exemplary embodiment, noise prediction-based data detection is described with respect to a SERDES (serializer/deserializer) backplane primary channel subject to inter-symbol interference (ISI) noise and added cross-talk noise from other channels. Noise prediction-based data detection combines an added error component from inter-symbol interference (ISI) noise and an added error component from cross-talk noise into an overall noise prediction error term and cancels effects of residual ISI and cross-talk for various components of the exemplary embodiment.

Abstract: An attacker is prevented from obtaining information about the configuration of a computer system. Each of one or more revealing content elements that may be found in outgoing data transmitted by the computer system and that are capable of being used by the attacker to obtain the information about the configuration of the computer system is associated with one or more respective replacement content elements. Outgoing data to be transmitted by the computer system are then scanned for these one or more revealing content elements. A revealing content element found in the outgoing data is replaced by a replacement content element from the one or more replacement content elements associated with that revealing content element. This is done before the outgoing data is transmitted.

Abstract: A method and apparatus are disclosed for wireless communication among integrated circuit devices within a single enclosure. Each of a plurality of integrated circuit devices within a single enclosure has one or more antennas that permit wireless communication. A signal destined for one or more integrated circuit devices within the same enclosure is transmitted by the transmitting integrated circuit device using an associated antenna. The transmitted signal is received by the antennas of each destination integrated circuit device. The present invention provides for pin to pin wireless transmission and reception among at least two integrated circuit devices. A plurality of channels may be achieved using known multiplexing techniques, such as time division multiplexing or the transmission of multiple signals at different carrier frequencies or on different antennas.

Abstract: In a semiconductor substrate, a shallow trench isolation structure having a dielectric material disposed in voids of a trench-fill material and a method for forming the shallow trench isolation structure. The voids may be formed during a wet clean process after the dielectric material is formed in the trench. A conformal silicon nitride layer is formed over the substrate and in the voids. After removal of the silicon nitride layer, the voids are at least partially filled by the silicon nitride material.

Abstract: Techniques for testing a semiconductor memory device are provided. The memory device includes a plurality of memory cells and a plurality of row lines and column lines connected to the memory cells for selectively accessing one or more of the memory cells. The method includes the steps of: applying a first voltage to at least a given one of the row lines corresponding to at least a given one of the memory cells to be tested, the first voltage being selected to stress at least one performance characteristic of the memory device, the first voltage being different than a second voltage applied to the given one of the row lines for accessing at least one of the memory cells during normal operation of the memory device; exercising the memory device in accordance with prescribed testing parameters; and identifying whether the memory device is operable within prescribed margins of the testing parameters.

Abstract: One aspect provides a method of standardized data creation and analysis of semiconductor technology node characteristics. In one embodiment, the method includes: (1) designing at least one representative benchmark circuit, (2) establishing standard sensitization and measurement rules for delay and power for the at least one representative benchmark circuit and across corners in the technology nodes, (3) performing a simulation by sweeping through a range of values and at predetermined intervals across the corners, (4) extracting data from the simulation and (5) parsing and interpreting the data to produce at least one report.