Abstract: Disclosed is a novel method and apparatus for acquiring multiple capacitively sensed measurements from a circuit under test. Multiple digital sources are respectively connected to stimulate multiple respective first ends of multiple respective nets of interest. Respective second ends of the multiple respective nets of interest are capacitively sensed. The respective capacitively coupled signals are digitally sampled and shift correlated with respective expected digital signatures. If a high level of correlation is found for a given net, the net is electrically intact; otherwise, the net is characterized by either an open or some other fault that prevents it from meeting specification.

Abstract: The present invention relates to an apparatus for delivering ions to a vacuum chamber. The apparatus comprises an ionization chamber, an ionization region within the ionization chamber, a vacuum interface at a vacuum interface voltage and a vacuum chamber, wherein the ionization chamber communicates with the vacuum chamber through the vacuum interface. Sample is introduced into the ionization chamber from an electrospray assembly at approximately ground potential. Two electrodes are provided within the chamber such that three electric fields are generated, a first field extending from the electrospray assembly to the first electrode, a second field extending from the second electrode to the first electrode, and a third field extending from the second electrode to the vacuum interface. Ions are forced to travel through the fields in order before entering the vacuum chamber. In addition, the invention provides a method of delivering ions to a vacuum chamber.

Abstract: A semiconductor-device characteristic measurement apparatus includes first measuring means for measuring a first electrical characteristic of a device under test, second measuring means, switching means for switching between the first measuring means and the second measuring means such that one of the measuring means is connected to the device under test, and controlling means for controlling the switching means. The switching means includes switches that switch between a first wiring configuration for electrically connecting the first measuring means to the device under test and a second wiring configuration for electrically connecting the second measuring means to the device under test. The switching means is electrically connected to the device under test at a position closer to the device under test than the first measuring means and the second measuring means.

Abstract: A switch selectively provides one of a first input signal at a first frequency and a second input signal at a second frequency to an output terminal with low insertion loss and high isolation between the first and second input signals. The first input signal is received at a first input terminal and the second input signal is received at a second input terminal. A switching element electrically connects the first input terminal and the output terminal to provide the first input signal to the output terminal in a first state and isolates the first input terminal from the output terminal in a second state. A bias line is electrically connected to provide a control signal to the switching element to select between the first state and the second state. An AC coupled transmission line is electrically connected to the second input terminal and electrically connected between the switching element and the output terminal.

Abstract: A dual-axis optical encoder device is disclosed. The optical encoder includes a substrate having a first surface and a second surface opposite the first surface and a first optical encoder on the first surface of a substrate and a second optical encoder on the second surface of the substrate. Each optical encoder includes an optical emitter and an optical detector. The dual-axis optical encoder device provides, within a single device, the ability to acquire movement information on two different axes.

Abstract: Off-chip driver (OCD) NMOS transistors with ESD protection are formed by interposing an P-ESD implant between the N+ drain regions of OCD NMOS transistors and the N-well such that the P-ESD surrounds a section of the N-well. The P-ESD implant is dosed less than the N+ source/drain implants but higher than the N-well dose. In another embodiment, N-well doping is used along with P-ESD doping, where the P-ESD doping is chosen such that it counterdopes the N-well underneath the N+ drains. The N-well, however, still maintains electrical connection to the N+ drains. This procedure creates a larger surface under the area where the junction breakdown occurs and an increased radius of curvature of the junction. The P-ESD implant is covered by N-type on three sides creating better parasitic bipolar transistor characteristics.

Abstract: A receiver method and apparatus is presented. Signals are received from a high-voltage environment to a low-voltage environment using low-voltage devices, such as low-voltage FETs. A reference stage (i.e., first stage) provides the reference point for an input signal that is received into a second stage. The reference stage works in conjunction with the second stage to control the output of the second stage. The reference stage and the second stage communicate through floating voltage signals. The output of the second stage is an inverted signal that floats. A third stage receives the inverted signals and corrects the signal to a baseline (i.e., adds gain to the signal). The signal is then clipped by a clipping stage (i.e., fourth stage). The clipping stage clips the high-voltage signal so that it will operate with the devices in the low-voltage environment. A fifth stage is then biased with a low voltage and the clipped signal is shifted downwards. Lastly, an inverter (i.e.

Abstract: In one embodiment, a method comprises applying a stimulus signal to a reference frequency translation device (FTD) by a vector network analyzer during a calibration mode, wherein the reference FTD possesses equal conversion efficiency in forward and reverse directions and the reference FTD possesses unknown input and output reflection characteristics; measuring a response of the reference FTD; and determining forward and reverse transmission tracking error terms using data from the measured response and single-port error calibration terms.

Abstract: A printhead fluid supply system for use in ink-jet or pulse-jet type printers is described. A manometer feature may be used as a pressure gauge to maintain desired pressure at a printhead. Additional features that may be used in the invention including a supply tubing setup configured to avoid introduction of air into a printhead. The system may be configured to allow for replenishing printing fluid supply while the system is running. This may be accomplished using a secondary fluid supply, to replenish a primary, pressure-compensated fluid reservoir. The system may be used in any sort of ink-jet or pulsejet printing system, such as those commonly used in document production or in more specialized applications such as microarray production.

Abstract: A delay-locked loop (DLL) of an integrated circuit (IC) with testing circuitry and a method for testing a DLL. During test mode, a phase comparator of the DLL receives a test clock in place of the reference clock and determines the phase difference between the test clock and the dock fed back to the DLL from a clock buffer tree. A variable delay element of the DLL then shifts the reference clock in time by an amount that depends on that phase difference. The variable delay element can be exercised by varying the phase of the test clock with respect to the reference clock by a known phase offset to cause the variable delay element to produce a range of delays. Whether the variable delay element is functioning properly can be determined by checking whether the phase of the test clock is aligned with the phase of the feedback clock.

Abstract: An apparatus for controlling the position of a screen pointer for an electronic device having a display screen includes a light source for illuminating an imaging surface, thereby generating reflected images. An optical motion sensor generates digital images from the reflected images at a first frame rate. The motion sensor is configured to generate movement data based on the digital images. The movement data is indicative of relative motion between the imaging surface and the apparatus. The motion sensor is configured to modify the first frame rate to one of a plurality of alternate frame rates based on a current relative velocity between the imaging surface and the apparatus.

Abstract: Measurements for an eye diagram of a signal of interest are placed in a data structure that is examined to locate an eye opening of interest. The eye opening of interest has already been, or is subsequently, normalized into figure of merit units related to the operational voltage and timing requirements of the data receiver for that signal. The locations within the normalized eye opening may be taken as center locations for trial symmetric shapes that start out small and are enlarged until they first include locations not part of the normalized eye opening. The center of a largest such shape is mapped back into the units of the original eye diagram as optimum sampling parameters for data analysis equipment that uses the receiver to sample the signal once per unit interval to discover logical value. An alternative is to repeatedly remove the ‘outer layer’ of the normalized eye opening until only one location remains.

Abstract: An optical encoder device (100) comprises: an optical emitter (103) for emitting light, the optical emitter (103) having a light emission direction (E); an optical detector (104) for detecting light emitted by the optical emitter (103), the optical detector (104) having a light detection direction (D) which is different from the light emission direction (E); an optical element (109) for controlling an optical path (108) between the optical emitter (103) and the optical detector (104) such that light emitted by the optical emitter (103) can be detected by the optical detector (104); and a free area (113) in the optical encoder device (100) for accommodating a moveable optical encoding unit (112) comprising a plurality of alternating transparent and opaque encoding elements such that the plurality of alternating transparent and opaque encoding elements of the optical encoding unit (112) is able to affect the optical path (108).

Abstract: A temperature sensor apparatus comprises a pair of parallel circuit branches each including a pn semiconductor junction coupled in series to an impedance. The pn semiconductor junctions have different cross-sectional areas. An amplification stage comprises a CMOS input stage coupled respectively across each pn semiconductor junction and a FET transistor output stage (coupled to a load impedance) that generates an amplified output signal corresponding to the pn semiconductor junction temperature.

Abstract: A switch includes a switching element, a substrate, a lid and a thickfilm dielectric. The substrate has a plurality of signal conductors formed thereon, at least some of which are in contact with the switching element. The lid covers the switching element and has a perimeter that intersects at least some of the signal conductors. The thickfilm dielectric is printed on the substrate below the perimeter of the lid, and the lid is mounted on the thickfilm dielectric.

Abstract: A two-dimensional photonic crystal resonator apparatus in which the power of light coupled out of the apparatus in one direction is greater than the power of light coupled out of the apparatus in the opposite direction The apparatus has a photonic crystal slab waveguide structure having a waveguide and a resonator in the vicinity of the waveguide such that light propagated through the waveguide is extracted from the waveguide through the resonator and is coupled out of the plane of the apparatus. The apparatus has upper and lower cladding layers on the photonic crystal slab waveguide structure having different indices of refraction, and the power of light coupled out of the apparatus in the direction of the cladding layer having the higher index of refraction is greater than the power of the light coupled out of the apparatus in the direction of the cladding layer having the lower index of refraction.

Abstract: A method and apparatus for testing a device using transition timestamp are used to evaluate output signals from the device. The method comprises the steps of performing timing tests on a signal from the device; and independently carrying out bit-level tests on a signal from the device. The independent timing tests and bit-level tests can be performed in parallel. The bit-level tests and apparatus comprise iteratively measuring a coarse timestamp for a transition in the signal and comparing the measured coarse timestamp to an expected timestamp to determine whether the device meets specifications. Whether the device meets specifications depends on whether, during the comparison step, the presence of a bit-level fault is detected. The apparatus and method may comprise Skew Fault detection, Bit Fault detection, No Coverage Warning detection and/or Drift Fault detection. An automatic testing system for testing devices comprises subsystems that incorporate the apparatus and method.

Abstract: An apparatus includes a device under test, a network analyzer, an internal amplifier, a first switch, a second switch, a third switch, a first air-line directional coupler, and a first attenuator. A method of characterization measurement includes providing a harmonics signal from the device under test to a spectrum analyzer, providing a generated signal and a reflected signal to a first receiver disposed within a network analyzer, and recording a parameter deviation of the network analyzer.

Abstract: A heterojunction bipolar transistor (HBT), comprises a collector formed over a substrate, a base formed over the collector, an emitter formed over the base, and a tunneling suppression layer between the collector and the base, the tunneling suppression layer fabricated from a material that is different from a material of the base and that has an electron affinity equal to or greater than an electron affinity of the material of the base.

Abstract: A signal synthesizer includes a high frequency offset stage having a high frequency offset source and frequency translation element in the feedback path of a dual-oscillator offset loop synthesizer. The signal synthesizer achieves low phase noise via noise cancellation when used to provide the first local oscillator of a spectrum analyzer and when the second local oscillator of the spectrum analyzer provides the high frequency offset source to the signal synthesizer.