Abstract: In one aspect, a circuit system includes a logic circuit and a bias circuit. The logic circuit includes one or more current mode logic gates each of which is operable to steer a respective tail current to produce an output voltage swing. The bias circuit is operable to maintain the voltage swing of each current mode logic gate independent of changes in tail current level. In another aspect, the circuit system includes a switching speed reference circuit that is operable to detect intrinsic switching speeds of the one or more current mode logic gates. In another aspect, the circuit system includes a tail current adjustment circuit that is operable to dynamically adjust the current mode logic gate tail currents to maintain logic gate switching speed in correlation with a reference clock frequency.

Abstract: A method and system to arbitrate requests of a plurality of ports of an interconnect device are provided. Every port receives combined pending request data that includes a pending request indicator associated with each of the plurality of ports. Each pending request indicator specifies whether a corresponding port has a pending request that needs to be submitted to a request bus of the interconnect device. Further, at each port, a turn to submit a request to the request bus is allocated to one of the plurality of ports based on the combined pending request data, a set of values stored in a mask register and a priority scheme associated with the plurality of ports.

Abstract: An HBT having an InP collector, a GaAsSb base and an InP emitter in which the base is constructed using a thin layer of GaAsSb. The thin base layer can be constructed of a GaAsSb material with a composition having a bulk lattice constant that matches the bulk lattice constant of the material of the collector. The thickness of the GaAsSb base layer is less than 49 nm, and preferably less that about 20 nm. Alternatively, the thin base layer is of a GaAsSb composition that includes a higher As content, resulting in a low conduction band energy discontinuity at the emitter-base junction. Such a GaAsSb base layer has a lattice constant that conforms to the lattice constant of the collector because it is thinly grown so as to be pseudomorphically “strained” over the collector. A high base doping level is used to reduce the sheet resistivity and lower the base series resistance that results from the thinly grown base layer.

Abstract: The invention relates to a method of tuning a laser, comprising the steps of: providing a laser beam to an external cavity, the laser beam traveling through material along a path between a cavity end element and a tuning element, the path having an optical path length, selecting at least one mode of the laser by introducing a dispersion element in the path of the laser, rotating the tuning element about a pivot axis theoretically defined by the intersection of the surface planes of the cavity end element, the dispersion element and the tuning element to tune the laser, changing the optical path length of the path in order to at least partly compensate a shift between the real position of the pivot axis and the theoretically defined position.

Abstract: A method and apparatus for coordinating program execution in a site controller with pattern execution in a tester executes the pattern in the tester and a pattern interruption instruction. The pattern interruption instruction causes the tester to write to a service request register in the site controller specifying a value that specifies a requested subroutine and a data source. The site controller initiates execution of the requested subroutine in the site controller using the specified data source.

Abstract: A modular system interface is provided. The apparatus includes a main panel that is configured to be attached to a rack and includes a plurality of cut-outs. A plurality of sub-panels are configured to be attachable to the main panel, spanning across the respective cut-out. Each sub-panel supports one predetermined type of connector. The present invention can also be viewed as a method for providing a modular system interface. In this regard, the method can be broadly summarized by the steps of providing a main panel configured to be attachable to a rack and including a plurality of cut-outs. The method includes providing a plurality of sub-panels configured to be attachable to the main panel across a respective the cut-out, wherein each sub-panel supports a predetermined type of connector.

Abstract: Integrated circuits (ICs) are provided. A representative IC includes a first pad that incorporates a first driver and a first receiver, with the first driver being configured to provide a first pad output signal to a component external to the IC, and the first receiver being configured to receive a first pad input signal from a component external to the IC. A first test circuit also is provided that is internal to the IC. The first test circuit is adapted to provide information corresponding to the driver strength of the first pad. Systems, methods, computer-readable media and other ICs also are provided.

Abstract: Signal communication structures and methods for making the same are provided. One embodiment of the present invention comprises a signal communication structure. The structure comprises a signal communication element having a signal communication surface, an integrated circuit chip, and a substrate. A surface of the signal communication element other than the signal communication surface is physically coupled to a surface of the integrated circuit chip. In addition, another surface of the integrated circuit chip is communicatively coupled to the substrate. Furthermore, the size of the signal communication surface is greater than the size of the surface of the integrated circuit chip to which the signal communication element is physically coupled.

Abstract: A system and method for testing an integrated circuit (IC) by transient signal analysis includes a comparison circuit that is configured to generate a comparison signal from an IC transient signal and a reference signal. Circuitry operationally coupled to the comparison circuit manipulates the comparison signal to generate a first output waveform area indicative of an absolute area of positive and negative portions within the comparison signal. The comparison circuit and the circuitry may include seven operational-amplifiers (op-amps) or ten op-amps. As a further processing sequence, a second output waveform area that is indicative of an absolute area of positive and negative portions within a second comparison signal is generated. In one embodiment, a first value representing the first waveform area and a second value representing the second waveform area are plotted to determine if the plotted X-Y coordinate falls within a predefined standard for determining the pass/fail status of the IC.

Abstract: The number of LIMMS devices in an assembly is increased by stacking multiple layers of LIMMS devices on top of one another, and interconnecting those device layers at an array of solder pads using solder balls. Each device layer uses vias to bring the needed conductors to the array of solder pads. All signals for the entire multi-layer assembly can be routed through the bottom LIMMS device layer to pass, through another array of solder pads onto a “mother substrate” of ceramic or other material that carries the multi-layer assembly. Alternatively, signals may enter or leave the upper LIMMS device layer by way of a flexible printed circuit harness. Vias may pass, either directly or by “dog legs” on interior surfaces, completely through the bottom LIMMS device layer, and through other device layers as needed.

Abstract: For drivers of different sizes driving signal lines of different lengths, maximum transition time constraints are compared to signal transition times to determine whether a potential noise problem exists with respect to the signal lines. Each driver size has a maximum line length and a maximum transition time associated with it. These maximum transition time constraints are used to determine whether the signal lines connected to respective drivers in the IC will have potential noise problems associated with them. For each signal line in the IC design, the signal transition time is determined and compared to the maximum transition time constraint. If the signal transition time exceeds the maximum transition time constraint, a potential noise problem exists with respect to the signal line.

Abstract: Ion guides and systems and methods for involving the use of ion guides are disclosed. Briefly described, one exemplary system, among others, includes an ion guide. The ion guide includes a first structure and a second structure. The second structure is coaxially disposed within the first structure. The second structure includes at least three groups of opening the through a wall of the second structure that are distributed around a circumference of the second structure. In addition, at least one of the group of openings is offset from the other groups of openings by a multiple of a constant rotation angle around the circumference of the second structure.

Abstract: A scheme (systems and methods) for passively aligning one or more optical devices with a corresponding number of optical lenses in an accurate and efficient manner is described. By this approach, the invention avoids the often labor-intensive and costly steps required by conventional active alignment techniques that attempt to align the optical devices to the optical fibers. In one aspect, an optoelectronic device includes an optical device system, an optical lens system and a plurality of solder bumps disposed therebetween. The optical device system includes an optical device substrate supporting one or more optical devices and a solderable metallization pattern having a spatial arrangement with respect to the one or more optical devices. The optical lens system includes one or more optical lenses and a device bonding surface supporting a solderable metallization pattern having a spatial arrangement with respect to the one or more optical lenses.

Abstract: A preamplifier includes a detector to detect an input optical power level and convert the detected input optical power level into an input current. The preamplifier also includes a transimpedance amplifier that provides a gain for the input current received from the detector. A dummy transimpedance amplifier is provided to supply a reference voltage. The dummy transimpedance amplifier has a structure similar to that of the transimpedance amplifier. A unity gain buffer is used to reduce the output impedance of the reference voltage and to output a bias voltage to both the transimpedance amplifier and the dummy transimpedance amplifier. This bias voltage can make the gate-controlled MOSFET working in its triode region, and the load resistance of the core amplifier can be easily controlled such that the gain and bandwidth of the core amplifier can be widely controlled. This results in the preamplifier having a high stability while its feedback resistor is controlled to achieve wide dynamic range.

Abstract: A circuit and method that maintains the impedance matching characteristics of a common output driver while compensating for the high-frequency signal attenuation inherent in printed circuit board traces and other integrated circuit signal transmission media are disclosed. The circuit includes a pre-emphasis driver configured in parallel with a standard output driver. The pre-emphasis driver is a tri-statable device which mirrors a received logic input when in an “on” state and provides a high output impedance with no signal content when in an “off” state. The pre-emphasis driver is controlled by a pre-emphasis control signal configured such that the pre-emphasis driver can inject high-frequency signal components into a transmission line for a portion of a clock cycle.

Abstract: An image sensor. The image sensor array includes a substrate. An interconnect structure is formed adjacent to the substrate. An amorphous silicon electrode layer is adjacent to the interconnect structure. The amorphous silicon electrode layer includes electrode ion implantation regions between pixel electrode regions. The pixel electrode regions define cathodes of an array of image sensors. The electrode ion implantation regions provide physical isolation between the pixel electrode regions. The cathodes are electrically connected to the interconnect structure. An amorphous silicon I-layer is adjacent to the amorphous silicon electrode layer. The amorphous silicon I-layer forms an inner layer of each of the image sensors. A transparent electrode layer is formed adjacent to the image sensors. An inner surface of the transparent electrode is electrically connected to anodes of the image sensors and the interconnect structure.

Abstract: Once an eye diagram measurement is begun and there is an eye diagram displayed, different on-screen measurement tools may be used singly, or in combination. Each measurement involves indicating with cursors and line segments regions of the eye diagram that are of interest, and a parameter or parameters associated with each measurement tool in use is reported in a (usually) separate area of the display. An Eye Limits measurement allows the specification of a point within an eye diagram, whereupon it finds and reports the eye diagram coordinates first encountered along horizontal and vertical lines extended from the selected point (i.e., “eye opening” size). The coordinates of the point itself are also reported. A Four Point Box measurement allows the construction on the eye diagram of a rectangle having sides parallel to the coordinate axes of the eye diagram.

Abstract: A photonic crystal drop filter apparatus and a method for tuning a photonic crystal drop filter. The photonic crystal drop filter has a photonic crystal having first waveguide for transmitting light having a frequency within a bandgap of the photonic crystal, and a second waveguide. The second waveguide is connected to the first waveguide by a resonant cavity for extracting at least one wavelength of the light transmitted by the first waveguide and redirecting the extracted light to the second waveguide. A tuning device is included in the apparatus to tune the wavelength of the extracted light over a full range of wavelengths. The apparatus is particularly suitable as an extraction device for optical communications systems such as a WDM communications system wherein it is necessary to extract one or more carrier signals from a plurality of carrier signals.

Abstract: A multiplexer for use with switching apparatus for data communication networks. The multiplexer topology includes two or more groupings, or sections, each containing a plurality of individual channels. Each of the channels has an input buffer amplifier and an output Ft-doubler circuit. The outputs of all of the channels within a each particular channel section are connected in parallel relation, and fed to respective common-base transistor amplifiers. The outputs of all of the common-base amplifiers for each channel section, in turn, are connected in parallel and fed to the inputs of a pair of emitter-follower amplifiers. Through the use of selectively actuated current sources, each multiplexer channel is normally biased off, unless that channel is selected for a switching operation. Bleeder current sources are applied to the emitters of the common-base amplifiers to reduce output jitter from the channels which are biased off.

Abstract: Sampling techniques and circuits for a waveform measuring instrument. The sampling techniques and circuits process a series of digital signal samples through a set of sample extractors and subsequently process the extracted digital signal samples. The set of sample extractors include a uniform decimator, a low frequency dither decimator, and a digital peak detector. The uniform decimator extracts a uniform decimated sample value for each decimated sample interval in a series of decimated sample intervals. The low frequency dither decimator extracts a low frequency dither decimated (random) sample value for each decimated sample interval in a series of decimated sample intervals. The digital peak detector extracts a maximum sample value and a minimum sample value for each decimated sample interval in the series of decimated sample intervals.