Patents Assigned to Agilent Technologies
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Patent number: 6435882Abstract: Socketable flexible circuit based electronic device modules and sockets for electrically and mechanically connecting the electronic device modules to an interconnect substrate are described. The systems provide ways in which the electronic device module may be positioned accurately and securely on an interconnect carrier, while allowing the electronic device modules to be replaced easily without having to resort to laborious desoldering and resoldering operations to remove the modules and connect new modules in their place.Type: GrantFiled: July 27, 2001Date of Patent: August 20, 2002Assignee: Agilent Technologies, Inc.Inventor: David S. Pitou
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Patent number: 6436488Abstract: Method of depositing a layer of amorphous silicon film on a substrate at a very fast deposition rate while maintaining superior film quality. A plasma volume in a process chamber is defined. A total flow rate of a mixture of gases introduced into the chamber is also defined. The total flow rate is the sum of the flow rates of the respective gases in the mixture. Next, a process parameter that includes the plasma volume and total flow rate is defined. The process parameter is then maintained in a first predetermined relationship with a predetermined value during the deposition of the amorphous silicon film.Type: GrantFiled: June 12, 2000Date of Patent: August 20, 2002Assignee: Agilent Technologies, Inc.Inventors: Jeremy A Theil, Gerrit J Kooi, Ron P Varghese
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Patent number: 6437587Abstract: A test fixture for performing in-circuit testing of a printed circuit assembly may comprise a board having a front surface and a back surface. A probe assembly also having a front surface and a back surface is mounted to the board so that the back surface of the probe assembly is adjacent the front surface of the board. The probe assembly includes at least one front surface contact pad positioned on the front surface of the probe assembly that is electrically connected to at least one back surface contact pad positioned on the back surface of the probe assembly. A first board pad positioned on the front surface of the board makes electrical contact with the back surface contact pad on the back surface of the probe assembly. An electrical conductor operatively associated with the board electrically connects the board pad to an input/output pad that is also provided on the board.Type: GrantFiled: November 4, 1999Date of Patent: August 20, 2002Assignee: Agilent Technologies, Inc.Inventors: Fred Hartnett, Terry Conner
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Patent number: 6438734Abstract: A method for operating a computer to find elementary loops in a strongly connected component of a graph. In the basic method, the computer identifies a starting vertex from the vertices of the strongly connected component that have not been examined as a possible starting vertex for an elementary loop and which are not contained in any elementary loop discovered thus far. The vertices of the strongly connected component are then searched for a path starting and ending on the identified vertex. If the search finds a path starting and ending of the identified vertex, the path is recorded as an elementary loop. This process is repeated until no starting vertex can be identified. To improve the efficiency of the search process, the computer identifies vertices that are the starting vertex for a paths that are shared by more than one elementary loop. The shared paths are stored separately and used to avoid searching the vertices of the path more than once.Type: GrantFiled: October 6, 1997Date of Patent: August 20, 2002Assignee: Agilent Technologies, Inc.Inventor: Dingqing Lu
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Patent number: 6437012Abstract: A low-swelling, highly crosslinked, macroporous polystyrene resin containing functional groups which are capable of selectively binding to reaction impurities, such as excess reactant or reaction by-products, which are contained in a reaction medium. The reaction impurities can thereby be efficiently removed from the reaction medium, providing a convenient method for product purification.Type: GrantFiled: October 27, 1999Date of Patent: August 20, 2002Assignee: Agilent Technologies, Inc.Inventor: Qunjie Wang
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Patent number: 6438373Abstract: A system and method are disclosed for determining a level of quality of a communications medium having an indeterminate delay. The communications medium communicatively couples a transmitting station and a receiving station. The transmitting station transmits over the communications medium a measurement sequence including a synchronization sequence followed by a measurement sample. The transmitted measurement sample has a predetermined beginning point, which is identified by the transmitted synchronization sequence. The receiving station receives over the communications medium the measurement sequence including the synchronization sequence followed by the measurement sample. The receiving station determines from the received synchronization sequence the beginning point of the received measurement sample. The transmitted measurement sample and the received measurement sample are then compared according to respective beginning points to determine the level of quality of the communications medium.Type: GrantFiled: February 22, 1999Date of Patent: August 20, 2002Assignee: Agilent Technologies, Inc.Inventors: Kenneth R. Gulledge, Edward Kryszkiewicz, Henry Ward Anderson, Robert Andrew Grom
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Publication number: 20020109354Abstract: The invention concerns a tube fitting (20) for providing a sealed flow connection between an open-ended duct (23) that extends along the longitudinal axis (22) of a tube (21) and an open-ended duct (26) of a base element (25), for liquid separation technology, in particular for analytical or preparative HPLC. The tube fitting (20) has a ring-shaped thrust piece (27) with a receptacle (28) for the tube (21) and a ring-shaped, spring-elastic compensating element (30) with a receptacle (31) for the tube (21). The tube fitting (20) further comprises a fastening element (35) that can be fastened tightly to the base element (25). The tube (21) preferably provides a ring flange (36) on its end (24) connected to the base element (25) that protrudes from the longitudinal axis (22) of the tube (21). When sealed, the base element (25), the thrust piece (27), the compensating element (30) and the tube (21) can be braced by means of the fastening element (35) under elastic deformation of the compensating element (30).Type: ApplicationFiled: January 25, 2002Publication date: August 15, 2002Applicant: Agilent Technologies, Inc.Inventor: Bernhard Dehmer
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Publication number: 20020109509Abstract: The present invention concerns a modular, portable device (1) to measure or test components in optical networks. It contains a base module (2) with base electronics, which features controls and a display device on the front; at least one function module (5, 6), which is attached by means of a mechanical interface to the outside of the back (4) of the base module (2), and contains a functional unit with measurement or test electronics, which work together with the base electronics through a functional interface, wherein the function module (5, 6) is detachably joined to the base module (2) and, depending on the application, may be replaced with another function module (5, 6) with another functional unit.Type: ApplicationFiled: February 1, 2002Publication date: August 15, 2002Applicant: Agilent Technologies, Inc.Inventors: Jochen Ziegler, Ralf Haefner, Alf Clement
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Patent number: 6433576Abstract: A circuit for altering a chip pad signal incorporates a primary driver that is configured to deliver a chip pad signal to an IC package. The circuit also is configured to cooperate with a second signal and a third signal, with the second signal having a voltage higher than the voltage of the first logic high, and the third signal having a voltage lower than the voltage of the first logic low. So configured, the primary driver may selectively deliver a second logic high, which has a voltage higher than the voltage of the first logic high, to the IC package, and may selectively deliver a second logic low, which has a voltage lower than the voltage of the first logic low, to the IC package. Electronic devices, systems and methods also are provided.Type: GrantFiled: August 3, 2001Date of Patent: August 13, 2002Assignee: Agilent Technologies, Inc.Inventor: Jason Harold Culler
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Patent number: 6433780Abstract: An optical mouse images as an array of pixels the spatial features of generally any micro textured or micro detailed work surface below the mouse. The photo detector responses are digitized and stored as a frame into memory. Motion produces successive frames of translated patterns of pixel information, which are compared by autocorrelation to ascertain the direction and amount of movement. A hold feature suspends the production of movement signals to the computer, allowing the mouse to be physically relocated on the work surface without disturbing the position on the screen of the pointer. This may be needed if the operator runs out of room to physically move the mouse further, but the screen pointer still needs to go further. The hold feature may be implemented with an actual button, a separate proximity detector or by detecting the presence of a characteristic condition in the digitized data, such as loss of correlation or velocity in excess of a selected limit.Type: GrantFiled: January 2, 2001Date of Patent: August 13, 2002Assignee: Agilent Technologies, Inc.Inventors: Gary B. Gordon, Derek L. Knee, Rajeev Badyal, Jason T. Hartlove
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Patent number: 6433713Abstract: A multislope, continuously integrating analog-to-digital converter can operate in either a conversion mode or a calibration mode. During the calibration mode, a calibration factor is calculated for use during the conversion mode. When applied to the conversion mode, the calibration factor corrects for errors in the conversion process.Type: GrantFiled: May 31, 2001Date of Patent: August 13, 2002Assignee: Agilent Technologies, Inc.Inventor: Philip B. Fuhrman
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Patent number: 6429466Abstract: A method for growing a crystalline layer that includes a first material on a growth surface of a crystalline substrate of a second material, wherein the first material and the second material have different lattice constants. A buried layer is generated in the substrate such that the buried layer isolates a layer of the substrate that includes the growth surface from the remainder of the substrate. The second material is then deposited on the growth surface at a growth temperature. The isolated layer of the substrate has a thickness that is less than the thickness at which defects are caused in the crystalline lattice of the first material by the second material crystallizing thereon. The buried layer is sufficiently malleable at the growth temperature to allow the deformation of the lattice of the isolated layer without deforming the remainder of the substrate. The present invention may be utilized for growing III-V semiconducting material layers on silicon substrates.Type: GrantFiled: January 29, 2001Date of Patent: August 6, 2002Assignee: Agilent Technologies, Inc.Inventors: Yong Chen, Scott W. Corzine, Theodore I. Kamins, Michael J. Ludowise, Pierre H. Mertz, Shih-Yuan Wang
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Patent number: 6429799Abstract: A method and apparatus converts an analog signal into a digital representation. The method comprises the steps of generating a quantity N of time-varying reference signals, where N is an integer greater than or equal to one, comparing an amplitude of the analog signal to an amplitude of each of the reference signals to determine whether the analog signal amplitude is greater than, less than or equal to reference signal amplitudes, and producing a timestamp each time the analog signal and reference signal amplitudes are equal. The apparatus comprises a reference signal generator and a quantity N of comparators, each of the comparators being connected to receive the analog signal, separately to receive a different one of the reference signals, and to produce a digital signal. The analog signal may be reconstructed from the digital representation.Type: GrantFiled: July 14, 2001Date of Patent: August 6, 2002Assignee: Agilent Technologies, Inc.Inventors: Linda Argon Kamas, Jochen Rivoir
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Patent number: 6430230Abstract: In a method for encoding payload bits for transmission over communications link, data and control information are assembled into n-bit data words, where n is an even number and words for control information are constrained to have zero disparity (equal numbers of binary zero and one digits). The n-bit data words are then encoded into n+2-bit code words by adding a two-bit label; for words carrying control information the label has a value of 10. For other data words the disparity is evaluated; if it is zero, the label bits are 01; if the disparity is non-zero and opposite in sense to the running digital sum of the code words transmitted already, the label bits are 11; otherwise, the data word is inverted, and the label bits are 00.Type: GrantFiled: June 30, 1999Date of Patent: August 6, 2002Assignee: Agilent Technologies, Inc.Inventors: David George Cunningham, Alistair Neil Coles
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Patent number: 6429683Abstract: An apparatus and method of shifting a low-voltage-swing digital signal to a signal of the same polarity with a relatively higher voltage swing are described which eliminate static current consumption by way of a feedback circuit and a pull-up device. By the use of embodiments according to the invention, little power is consumed, and hot electron injection as a mechanism for FET degradation is of little concern. Additionally, no specialized reference voltage is necessary, and precise layout of the circuit is not critical to proper circuit performance.Type: GrantFiled: August 16, 2000Date of Patent: August 6, 2002Assignee: Agilent Technologies, Inc.Inventors: Darrin C. Miller, Brian C Miller
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Patent number: 6430338Abstract: An optical measuring device includes an optical detector for measuring an incident optical signal coupled to the detector by an optical fiber. The optical fiber and/or the optical detector comprise an interface between optical media with different refractive indices, e.g., a boundary surface, face or facet. The interface is angled with respect to the incident optical signal to reduce reflection in the direction of the incident optical signal. Because light transmitted with a polarization perpendicular to the plane of incidence of the optical signal has an intensity substantially equal to the intensity of light transmitted with a polarization parallel to the plane of incidence of the optical signal, the incident optical signal transmitted through the interface is substantially independent of the polarization direction of the incident optical signal.Type: GrantFiled: May 11, 2000Date of Patent: August 6, 2002Assignee: Agilent Technologies, Inc.Inventor: Siegmar Schmidt
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Patent number: 6430078Abstract: A circuit and method of implementing a digital read-only memory (ROM) utilizes a means for selectively driving one of two complementary logic state signal lines to a voltage reference upon a readout signal for an addressable bit becoming active. Each complementary logic state signal line represents one of two logic states. The logic state of the addressed bit is determined by which of the two complementary logic state signal lines is driven. The logic level of each complementary logic state signal line is then inverted and driven onto the other so that both signal lines will be driven to their proper logic state, thereby allowing either signal line to be used in ascertaining the logic state of the bit being addressed.Type: GrantFiled: July 3, 2001Date of Patent: August 6, 2002Assignee: Agilent Technologies, Inc.Inventors: Victoria Meier, Robert J. Martin
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Patent number: 6429511Abstract: A microcap wafer-level package is provided in which a micro device is connected to bonding pads on a base wafer. A peripheral pad on the base wafer encompasses the bonding pads and the micro device. A cap wafer has gaskets formed thereon using a thick photoresist semiconductor photolithographic process. Bonding pad gaskets match the perimeters of the bonding pads and a peripheral pad gasket matches the peripheral pad on the base wafer. Wells are located inside the perimeters of the bond pad gaskets and are formed to a predetermined depth in the cap wafer. The cap wafer is then placed over the base wafer to cold weld bond the gaskets to the pads and form a hermetically sealed volume between the bonding pad gaskets and the peripheral pad gasket. The cap wafer is then thinned below the predetermined depth until the wells become through holes that provide access to the bonding pads inside the package, but outside the hermetically sealed volume, for connecting wires from a micro device utilizing system.Type: GrantFiled: October 1, 2001Date of Patent: August 6, 2002Assignee: Agilent Technologies, Inc.Inventors: Richard C. Ruby, Tracy E. Bell, Frank S. Geefay, Yogesh M. Desai
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Patent number: 6428957Abstract: Systems, tools and methods of assaying biological material are used to perform complex sandwich hybridization assays. The tools used comprise biological solution probes that are customized for each assay. The solution probe comprises a first region for hybridizing to a probe, in a generic set of capture probes on a universal assay apparatus, and a second region for hybridizing to a target in a sample. The solution probe assembles the target to the assay apparatus by hybridizing the second region to the target and the first region to the capture probe. In array assays, one or more biological samples, having one or more targets per sample, can be multiplexed on the same universal array comprising the generic set of capture probes in an array pattern of features on the substrate. The customized solution probe addresses and assembles a predetermined target-sample combination onto the array at a corresponding capture probe address location.Type: GrantFiled: November 8, 1999Date of Patent: August 6, 2002Assignee: Agilent Technologies, Inc.Inventor: Glenda C. Delenstarr
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Publication number: 20020101251Abstract: For measuring a capacitance with high accuracy, a capacitance measuring apparatus includes a voltage source with a current limiting function for applying different voltage values to the capacitance, and an integrator capable of continuous integrating operation for repeatedly integrating a current flowing through the capacitance at given periodic intervals. There is also disclosed a capacitance measuring method that is carried out by the capacitance measuring apparatus.Type: ApplicationFiled: November 2, 2001Publication date: August 1, 2002Applicant: Agilent Technologies, Inc.Inventor: Akira Shimizu