Patents Assigned to Agilent Technologies
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Patent number: 6196971Abstract: A chord propagation velocity measurement (CPVM) system is used in connection with, for example, a brightness-mode (B-mode) or doppler ultrasound imaging system. The CPVM system monitors ultrasound data provided to it by the ultrasound imaging system and enhances the functionality of the ultrasound imaging system by providing a chord propagation velocity (CPV) associated with a body region, such as a blood vessel in a living thing. The CPV is indicative of the stiffness of the body region. In architecture, the CPVM system includes a tissue processor connected to the scanner of the ultrasound system designed to analyze each acoustic scan line and to determine a category (type of region, for example, blood or tissue) for each point along each acoustic scan line. A display produces an image generated from acoustic scan lines. A user input mechanism permits a user to identify a region of interest in the image. The tissue processor produces samples based upon the region of interest in the image.Type: GrantFiled: April 2, 1999Date of Patent: March 6, 2001Assignee: Agilent Technologies, Inc.Inventors: David M Prater, Joel Friedman
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Patent number: 6198292Abstract: A test unit for measuring crosstalk in twisted pair cable. The test unit has an output signal balance (OSB) circuit that compensates for parasitic capacitance at its output terminals. The OSB circuit has a voltage controlled capacitance connected in circuit with each output terminal to control the effective capacitance between the output terminals and ground. The bias voltage for the variable capacitances is calibrated by a method in which the voltage for one of the variable capacitors is held constant while the voltage for the other capacitor is varied in voltage levels. A test signal frequency sweep is applied to the test unit output terminals. First and second voltage values are obtained and a final bias voltage value is calculated from using these two values.Type: GrantFiled: July 20, 1999Date of Patent: March 6, 2001Assignee: Agilent Technologies, Inc.Inventors: James W Kirk, Ron Cook, Michael J Haley, Fanny I Mlinarsky
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Patent number: 6198096Abstract: A technique for analyzing ions by determining the time of flight of the ions from a source before detection at a detector. In the technique a series of pulses is generated according to an encoded sequence. Pulses from the series of pulses are selected to launch a plurality of packets of ions from the source, each of the selected pulses launching a packet of ions such that ions launched in the adjacent packets overlap prior to reaching the detector. At the end of the series another cycle of the series is generated again and some of the pulses in the series are selected in the another cycle to launch a plurality of packets of ions from the source. The cycles of pulse generation and selection to launch ions are repeated. The time of arrival of the ions of each packet in the detector is determined to obtain signals corresponding to overlapping spectra of the time of arrival of the packets of ions.Type: GrantFiled: December 22, 1998Date of Patent: March 6, 2001Assignee: Agilent Technologies, Inc.Inventor: Christian Le Cocq
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Patent number: 6198856Abstract: An improved optical switch allows for the testing, calibration and monitoring of optical switch points in an optical switching matrix. A test column and a test row of additional switch elements and optical paths enable the improved optical switch to provide testing, calibration and monitoring of each optical switch point in the optical switch matrix using a test input source and a test output receiver. The improved optical switch may also be used to test for the presence of light at any input and to inject a test signal into the matrix in order to test for the presence and quality of light at any output.Type: GrantFiled: April 16, 1999Date of Patent: March 6, 2001Assignee: Agilent Technologies, Inc.Inventors: Dale W. Schroeder, David K. Donald, Wayne V. Sorin, Shalini Venkatesh
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Patent number: 6198864Abstract: A demultiplexer includes a unitary optically transparent structure that utilizes focusing relay mirrors to relay a multi-wavelength beam of light among a series of wavelength-specific interference filters, with each filter separating out a specific wavelength component from the multi-wavelength beam. The relay mirrors are focusing mirrors, so that the demultiplexer can be operated with a non-collimated light beam in a manner that controls the potentially large angle of divergence of non-collimated light, while taking advantage of the small beam diameter in order to create a demultiplexer with greater miniaturization.Type: GrantFiled: November 24, 1998Date of Patent: March 6, 2001Assignee: Agilent Technologies, Inc.Inventors: Brian E. Lemoff, Lewis B. Aronson
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Patent number: 6198345Abstract: A polyphase filter passes a desired frequency and attenuates an image frequency in many communication systems. The invention is an error correction circuit that compensates the polyphase filter for low open loop gain operational amplifiers. When multiple polyphase filters are used in communication circuits on a single integrated circuit (IC), the open loop gain of the operational amplifiers is limited by the IC's ability to dissipate power. The error correction circuit reduces the dependency of the polyphase filter performance on the low open loop gain of its operational amplifiers and hence, on temperature and IC process parameters.Type: GrantFiled: December 21, 1999Date of Patent: March 6, 2001Assignee: Agilent Technologies, Inc.Inventor: Thomas Hornak
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Patent number: 6194924Abstract: A multi-function output driver that may be used with at least two types of busses includes a multiplexer that shifts calibration bits to the pull-down transistors. This shifting changes which transistors of the transistor array are turned on when the pull-down drive transistors are driving. By changing which transistors are turned on, the impedance of the driver is changed. This shifting is used with a disable function on the pull-up drive-transistors to allow the driver to be used as an end-of-line termination, an open-drain driver, or as a source-terminated driver.Type: GrantFiled: April 22, 1999Date of Patent: February 27, 2001Assignee: Agilent Technologies Inc.Inventors: M. Jason Welch, Brian Cardanha
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Patent number: 6195478Abstract: A planar lightwave circuit (PLC) is formed to include switching elements in which optical coupling among waveguides is determined by positions of displaceable members, such as micromirrors. Each switching element includes at least two light-transmitting waveguides extending along a waveguide substrate to a trench. The optical coupling between the waveguides of a switching element is dependent upon the optical characteristics exhibited at the trench. The displaceable device of a switching element has a transmitting position and a reflecting position. The displaceable device may be manipulated using microelectromechanical system (MEMS) techniques or techniques similar to those used in a dot matrix printer engine. The trench at the crosspoint of waveguides may include a liquid having a refractive index that closely matches the refractive index of the core material of the waveguides.Type: GrantFiled: September 28, 1999Date of Patent: February 27, 2001Assignee: Agilent Technologies, Inc.Inventor: Julie E. Fouquet
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Patent number: 6194743Abstract: A light emitting device constructed on a substrate. The device includes an n-type semiconductor layer in contact with the substrate, an active layer for generating light, the active layer being in electrical contact with the n-type semiconductor layer. A p-type semiconductor layer is in electrical contact with the active layer, and a p-electrode is in electrical contact with the p-type semiconductor layer. The p-electrode includes a layer of silver in contact with the p-type semiconductor layer. In the preferred embodiment of the present invention, the n-type semiconductor layer and the p-type semiconductor layer are constructed from group III nitride semiconductor materials. In one embodiment of the invention, the silver layer is sufficiently thin to be transparent. In other embodiments, the silver layer is thick enough to reflect most of the light incident thereon. A fixation layer is preferably provided over the silver layer.Type: GrantFiled: December 15, 1998Date of Patent: February 27, 2001Assignee: Agilent Technologies, Inc.Inventors: You Kondoh, Satoshi Watanabe, Yawara Kaneko, Shigeru Nakagawa, Norihide Yamada
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Patent number: 6194900Abstract: A miniaturized total analysis system with an in-line NMR detection compartment and an NMR rf microcoil detector is described for use in liquid phase analysis. The device is formed by microfabrication of microstructures in novel support substrates. The NMR detector coil may be fabricated directly in the support body at the point of detection or, alternatively, may be formed as part of a modular structure that is insertable into the device at the point of detection. In addition, an integrated device for sample preparation and NMR detection is provided comprising the miniaturized total analysis system and a miniature magnet configured to accept the miniaturized total analysis system, wherein the device is capable of generating an NMR spectrum. The invention herein is used for the analysis of small and/or macromolecular and/or other solutes in the liquid phase.Type: GrantFiled: June 19, 1998Date of Patent: February 27, 2001Assignee: Agilent Technologies, Inc.Inventors: Dominique M. Freeman, Sally A. Swedberg
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Patent number: 6193661Abstract: Disclosed is a system and method for generating two dimensional renderings on a display device of acoustic volumetric data that provides depth perception to the user. The system includes an acoustic data acquisition circuit, which includes a sonic transducer and other components, that generates and stores an acoustic data set from medium such as a human body, etc. A scan converter generates a perspective volumetric data set of the medium based upon the acoustic data set, and a single dimensional interpolator that generates at least one interpolated data set from the perspective volumetric data set. The perspective volumetric and interpolated data sets are processed by a compositor that generates two dimensional renderings of the perspective volumetric data set and the interpolated data sets. The system includes a display device which displays the two dimensional renderings in a predetermined fashion to provide depth perception to the viewer.Type: GrantFiled: April 7, 1999Date of Patent: February 27, 2001Assignee: Agilent Technologies, Inc.Inventors: David W Clark, Richard A Hager
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Patent number: 6191478Abstract: A demountable heat spreader assembly utilizing a unique retainer frame for demountably retaining a heat spreader having a flexible thermal interface material disposed in a cavity of the heat spreader is disclosed. The retainer frame allows a substrate having a flip chip IC mounted thereon to be snapped into the retainer frame. The heat spreader also snaps into the retainer frame and is positioned in the retainer frame so that the flexible thermal interface material contacts the IC with a slight interference. The flexible thermal interface material provides effective thermal coupling between the IC and the heat spreader and loose mechanical coupling between the IC and heat spreader. Thermomechanical stress caused by heating or cooling of the IC is reduced by the loose coupling between the IC and the flexible thermal interface material. The retainer frame allows for the heat spreader and the substrate to be removed and can be made from low cost materials such a plastic.Type: GrantFiled: June 7, 1999Date of Patent: February 20, 2001Assignee: Agilent Technologies Inc.Inventor: Kim H Chen
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Patent number: 6192496Abstract: An apparatus and method are provided for testing component tolerances of a device for testing integrated circuits. The testing device is generally characterized by a plurality of test connectors disposed at a test head, wherein each test connector carries electrical signals for a test channel. Further, each test channel generally corresponds to a circuit board that includes at least one driver and one receiver. In this general type of tester, a system is provided that includes a specialized DUT board that establishes a low impedance electrical connection (i.e., short) between electrical conductors of a first and second test connector. Through this low impedance path, a first driver from a first circuit board is directly connected (i.e., shorted) to a first receiver on a second circuit board. A controller is configured to control the first driver to output an electrical signal at a predetermined time.Type: GrantFiled: November 26, 1997Date of Patent: February 20, 2001Assignee: Agilent Technologies, Inc.Inventors: William R. Lawrence, David H. Armstrong
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Patent number: 6190322Abstract: Disclosed is a system and method for generating an ultrasound echo signal with reduced linear components. In one embodiment, the system comprises an excitation signal source configured to generate a first excitation signal and a second excitation signal, and a transducer coupled to the excitation signal source, the transducer being configured to emit a first asymmetric ultrasonic pulse in response to the first excitation signal and a second asymmetric ultrasonic pulse in response to the second excitation signal, the first and second asymmetric ultrasonic pulses being emitted into a medium.Type: GrantFiled: June 29, 1999Date of Patent: February 20, 2001Assignee: Agilent Technologies, Inc.Inventor: David W Clark
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Patent number: 6191433Abstract: An OLED display device and a method of fabricating the device utilize a patterned layer of conductive pads formed over a substrate to fabricate a cathode layer without the need to subsequently pattern the cathode layer to create individually addressable cathodes. The design of the OLED display device is such that the cathode layer is positioned below the anode layer. The OLED display device may be configured to emit light through the substrate or through the top layer, i.e., the anode layer. In a first embodiment, the conductive pads have sharp edges that effectively pattern the cathode layer when it is formed over the pads. In a second embodiment, the conductive pads do not include sharp edges. In this embodiment, the cathode layer is made of a composite material, which includes cathode components and non-conducting components.Type: GrantFiled: March 17, 2000Date of Patent: February 20, 2001Assignee: Agilent Technologies, Inc.Inventors: Daniel B. Roitman, Homer Antoniadis
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Patent number: 6191603Abstract: An integrated circuit having an embedded testing system. The integrated circuit has a plurality of chip input terminals and a plurality of chip output terminals and operates in a test mode and a normal mode. The integrated circuit includes a plurality of core modules and a test data bus. The test data bus has first and second conductors accessible from the chip input and output terminals, respectively. Each core module includes an access register for storing an access word, and a plurality of registers connected together as a first scan-chain having an input terminal for receiving data to be shifted into the registers and an output terminal for reading data shifted out of the registers. Each core module also includes a scan-in enable circuit and a scan-out enable circuit. The scan-in enable circuit connects the input terminal of the first scan-chain to the first conductor of the test data bus.Type: GrantFiled: January 8, 1999Date of Patent: February 20, 2001Assignee: Agilent Technologies Inc.Inventors: Fidel Muradali, Robert C. Aitken
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Patent number: 6191570Abstract: A method for testing node isolation on a circuit board. The method utilizes an automated test system having a plurality of test channels, wherein each test channel has a digital driver with a first input and a first output, and a digital receiver with a second output and a second input. The second input of the receiver is coupled to the first output of the driver, to a number of switches, and to a test probe. The test probe is configured to couple the driver and receiver to one of a plurality of nodes on a circuit board. The number of switches are configured to selectively couple the first output and second input to ground. During a node isolation test, each node of a test node group is coupled to one of the test channels. But for a selected node of the test node group, each node of the test node group is coupled to ground via the number of switches of the test channels coupled to the nodes.Type: GrantFiled: July 26, 1999Date of Patent: February 20, 2001Assignee: Agilent Technologies, Inc.Inventors: Kevin G. Chandler, Barry A. Alcorn, Bryan D. Boswell, John M. Heumann, Ed O. Schlotzhauer
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Patent number: 6191572Abstract: A mechanical press for testing printed circuit boards in conjunction with a conventional probe card testing assembly is presented. A press assembly attached to a press mount mounted over the probe card testing assembly includes a movable frame including a plate that is height-adjustable relative the movable frame and a plurality of synchronized force-applying members that are actuatable to extend the plate downward a predetermined distance with equal downward pressure across the plate. The plate is height-adjustable within the movable frame via four elongated rotatable screws that protrude through the upper surface of the press mount in order to moveably support the press assembly. Each screw has a timing belt pulley for synchronous power transmission disposed above the stationary frame upper surface. A timing belt or similar continuous belt or chain engages each belt pulley, thereby synchronizing the rotation of the screws.Type: GrantFiled: May 29, 1998Date of Patent: February 20, 2001Assignee: Agilent Technologies Inc.Inventors: Dwight Fowler, Chris R. Jacobsen
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Patent number: 6191683Abstract: Disclosed is a system and method to compare logical values. The system employs a field programmable gate array (FPGA) configured for comparing logical values. The FPGA includes a number of inputs to receive an N-bit sampled value from a target system, where N defines the number of bits in the N-bit sampled value. The FPGA also includes a number of lookup tables configured to receive an M-bit portion of the N-bit sampled value. These lookup tables generate a lookup table output in response to the M-bit portion. Finally, an AND operation is performed on the outputs of the lookup tables that generates an output indicating whether the particular N-bit logical value matches a particular desired value. Note that a single AND gate may be used or a number of AND gates may be used in place of the single AND gate. The tables within the lookup tables are generated based upon a desired logical value and a comparison mask value.Type: GrantFiled: August 31, 1999Date of Patent: February 20, 2001Assignee: Agilent Technologies, Inc.Inventor: Richard A. Nygaard, Jr.
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Patent number: 6192093Abstract: A method and system for receiving CIMT encoded data transmitted in simplex mode. The receiver (12) is adapted to receive a stream of digital data and analyze successive portions thereof to identify a predetermined pattern of data. The receiver (12) outputs the received digital data in response to a detection of the predetermined pattern of data and, in the alternative, outputs other data in response to a failure to detect the predetermined pattern of data. In the illustrative embodiment, the stream of digital data is transmitted as conditional invert master transition encoded simplex data. The receiver (12) includes a CIMT decoder (16) which analyzes the input data to identify a master transition therein. The receiver (12) uses a local clock to analyze successive portions of the received data stream and word alignment logic to identify a master transition therein.Type: GrantFiled: July 30, 1999Date of Patent: February 20, 2001Assignee: Agilent TechnologiesInventors: Benny W H Lai, Tony Lin, Charles L. Wang