Abstract: A circuit and method for reducing error in a delay locked loop (DLL) in which a plurality of outputs, each establishing a boundary between two consecutive phases, is accomplished by averaging an error present in one of the outputs over at least two phases established by the outputs. A pair of inverters are used to drive fight during a definable time period, which enables the circuitry to average the error over at least two phases, thus distributing the error that was present in one phase over at least two phases.

Abstract: An electrostatic discharge (ESD) protection device for coaxial systems ensures that center conductors of coaxial cables are discharged prior to insertion of the cables into a coaxial connector of an electronic instrument. The device includes a conductive mounting post fastened to the instrument and conductive hinge, pivotally mounted to an end of the post. The conductive hinge has a raised target area for contacting the center conductor of a conductive cable. Prior to insertion of the cable into the coaxial connector, the conductive hinge rests in a neutral position, obstructing access of the cable to the coaxial connector. When the cable is advanced toward the coaxial connector of an electronic instrument, the center conductor of the cable contacts the target area, thereby grounding the center conductor to the instrument through the conductive hinge and conductive mounting post.

Abstract: In general, the present invention is a system and method for interfacing signals with processing elements, such as microprocessors. The present invention utilizes a processing element, an electrical connection, a resistive device, a current sink, a first diode, a second diode, and a buffer. The electrical connection is coupled to the processing element, which is associated with an operating voltage. The resistive device is coupled to the electrical connection, and the first diode is coupled to the electrical connection and the current sink. An anode end of the first diode is coupled to the electrical connection between the resistive device and the processing element, and a cathode end of the first diode is coupled to the current sink. The buffer is coupled to the processing element, which transmits a voltage corresponding with the operating voltage of the processing element to the buffer. The second diode couples the buffer to the current sink.

Abstract: A defibrillator having one or more redundant systems each including functionally interchangeable components from which one component is selected for current operation. Manual or automatic selection of one component in each redundant system is made to form an operational defibrillator. Preferably, such selection is based on a real-time evaluation of the operational integrity of all operational components in a redundant system. Such real-time evaluations may be performed by monitoring systems within a controller, by an external test system within or external to the defibrillator or by self-test mechanisms internal to the operational components themselves. Factors such as user preferences, default component assignment, and predetermined arrangements of operational component combinations may be included in the selection determination along with the operational integrity of each operational component.

Abstract: An airflow director constructed for use with a separation column in a temperature-controlled air bath in a chromatographic oven cavity, wherein the airflow director includes at least a first baffle locatable with respect to the separation column and to the low pressure and high-pressure regions of the air bath, wherein the baffle is configured to direct air flow away from the high-pressure region before passing over the separation column. The temperature-controlled air thereby mixes with oven cavity air before passing over the separation column, which is thereby less subject to thermal gradients.

Abstract: The disclosed ultrasound imaging apparatus and method use a transducer array with a very large number of transducer elements or a transducer array with many more transducer elements than beamformer channels. The imaging apparatus includes a transmit array including a multiplicity of transducer elements allocated into several transmit sub-arrays, and a receive array including a multiplicity of transducer elements allocated into several receive sub-arrays. The apparatus also includes several intra-group transmit processors, connected to the transmit sub-arrays, constructed and arranged to generate a transmit acoustic beam directed into a region of interest, and several intra-group receive processors connected to the receive sub-arrays. Each intra-group receive processor is arranged to receive, from the transducer elements of the connected sub-array, transducer signals in response to echoes from the transmit acoustic beam.

Abstract: A distributed system with mechanisms and protocols for self-grouping of communication in the distributed system. A distributed system according to the present teachings includes a set of nodes and a set of group hubs that enable communication among the nodes. The group hubs and the nodes engage in a group identification protocol for determining a set of groupings of the nodes which are based on a topology of connections among the group hubs and the nodes. The group hubs include mechanisms for special handling of messages associated with the group identity protocol. The mechanisms and protocols for self-grouping are such that communication addressing is automatically determined by the nodes based on the topology of the distributed system.

Abstract: A method and apparatus for low cost set mapping in, for example, a computer graphics processor or communications device efficiently maps elements of one set into another set. When used in conjunction with a graphical display system the low cost set mapping logic enables a memory controller to efficiently communicate with a plurality of memory devices based upon a hierarchical computation scheme. The method and apparatus provide a pseudo-optimal mapping solution. By employing a pseudo-optimal mapping solution the low cost set mapping logic greatly reduces the computational resource required to perform the mapping operation.

Abstract: A stretch controller and a repeat controller allow for manipulation of graphical shapes in arbitrary angles. To stretch the graphic shape, a stretch distance and a stretch direction are received from a user. When the stretch direction is positive, then a determination is made as to vertices of the graphic shape are on a first side of a control line. The control line is at an arbitrary angle. This means that the control line does not have to be parallel to or orthogonal to an x-axis, but can be placed at a range of angles from 0 degrees to 180 degrees with respect to the x-axis. The vertices of the graphic shape, which are on the first side of the control line are moved the stretch distance in a direction orthogonal to the control line.

Abstract: A machine code generating system for improved pattern matching in a protocol analyzer. The code generating system includes a pattern relationship analysis phase and a pattern matching code generation phase. The pattern relationship analysis phase includes evaluating pairs of test patterns to determine the relationship that exists between each pair such as superset, subset, independent, external, and identical. The pattern matching code generation phase includes generating general pattern matching code in addition to generating specialized comparison code that is specific to the types of relationships that exist among a given set of patterns. The machine code that is generated, organizes the patterns into groups to minimize the number of pattern matching comparisons required to a minimum defined in the average case as the sum of the number of patterns and the maximum number of words per pattern.

Abstract: An amplifier/switch circuit includes a first circuit input, a second circuit input, a circuit output, an amplifier, a switching circuit and a DC blocking capacitor. The amplifier has an amplifier control input, a first amplifier output and a second amplifier output. The amplifier control input is connected to the first circuit input. The first amplifier output is connected to the second circuit input. The second amplifier output is connected to the circuit output. A switching circuit has a switch control input, a switch input and a switch output. The switch control input is connected to the circuit output. The control input is connected to the second circuit input. The DC blocking capacitor is connected between the amplifier control input of the first transistor and the switch input.

Abstract: Two wafers are bonded together through an annealing process that maintains temperatures at CMOS compatible levels (i.e., below 500 degrees Celsius). A layer of palladium (Pd) is formed on a first wafer. Preferably an adhesion layer of chromium (Cr) attaches the palladium layer to the first wafer. The palladium layer is engaged with silicon (Si) from a second wafer, and the engaged wafers are annealed to form a palladium-silicide (PdSi) bond between the palladium layer of the first wafer and the silicon of the second wafer. In addition to bonding the first wafer to the second wafer, the palladium-silicon bond may be used to form an electrical connection between the two wafers so that circuits on both wafers may communicate to one another through the palladium-silicon bond.

Abstract: The present invention is generally directed to a PVT compensated variable impedance output driver for driving a signal through a signal pad on a semiconductor device. In accordance with one aspect of the present invention, the output driver includes a plurality of p-channel field effect transistors (PFETs) electrically connected in parallel. A source node of each of the plurality of PFETs are electrically connected together, and a drain node of each of the plurality of PFETs are electrically connected together. The driver further includes a plurality of n-channel field effect transistors (NFETs) electrically connected in parallel. A source node of each of the plurality of NFETs are electrically connected together and a drain node of each of the plurality of NFETs are electrically connected together.

Abstract: A graphical user interface for use in a computer system is disclosed. The computer system includes an operating system responsive to one or more system calls. Each system call causes the operating system to process user inputs in a predetermined manner. In this aspect of the invention, the graphical user interface includes means for generating at least one dialog box request in response to a user input provided on the graphical user interface. The graphical user interface also includes a plurality of dialogs each constructed and arranged to control display of and interactivity with an associated dialog box opened on the graphical user interface in response to one or more of the dialog box control requests. A dialog box control system of the graphical user interface is responsive to a selected one of a plurality of dialog launch modalities, and is constructed and arranged to close open dialog boxes not having a predetermined relationship with the selected dialog box.

Abstract: The present invention is generally directed to a system and method for calculating the velocity, displacement and/or strain of a moving surface or web of material. ("Surface or web" is hereafter referred to simply as "web".) In accordance with one aspect of the invention, a system is provided having a first photosensor array disposed near the web of material and a second photosensor array disposed near the web of material, wherein the second photosensor array is spaced a distance "d" from the first photosensor array. A processing unit is coupled to both the first photosensor array and the second photosensor array and is configured to control or carry out functional operations and computations associated with the system.

Abstract: A method for increasing the layer density uniformity across a conductive layer, which comprises a plurality of functional blocks, of an integrated circuit is presented. Increased uniformity is achieved by tiling a plurality of capacitors in between the functional blocks. The configuration of the capacitor array and number of the capacitor cells in the array is arranged so as to provide approximate uniformity in the conductor-to-non-conductor density across the entire conductive layer. The capacitor array may be used to reduce power supply switching noise by coupling one or more of the capacitor cells making up the capacitor array between a high power rail and a low power rail.

Abstract: A method of assembling an optical device for coupling optical fibers to a corresponding number of input/output ports of a stack of optical elements includes utilizing at least one controllable multi-state optical element to selectively switch the optical coupling among the ports. The controllable multi-state element is one element within a stack of polarization-manipulating elements having a configuration that allows the condition of the multi-state element or elements to dictate the optical coupling among the ports. In the preferred embodiment, the multi-state element is a Faraday rotator. The method may be used in either or both of a quality control application or a fiber-to-port alignment application. In the quality control operation, the stack of polarization-manipulating elements is tested to verify proper operation with respect to separating and selectively recombining polarization components of input beams.

Abstract: A display device and a method of driving liquid crystals in an array of pixels of the display device include providing dual port memory cells that isolate write operations to the pixels from read operations within the pixels. Preferably, each pixel has an array of integrated dual port memory cells, with the number of cells in the array being equal to the number of bits per pixel within each frame of pixel data. The dual port memory cell may be an electrical series connection of a bit-storage device having write access circuitry (e.g., a write access transistor) on one side and read access circuitry (e.g., two read access transistors) on the opposite side. Such a series connection of devices enables the rate of driving the liquid crystal to be set independently from the rate of receiving pixel data at the pixels.

Abstract: An application specific integrated circuit for use with a circuit having particular electrical characteristic such as ringing or impedance. The circuit has an output pad with an output transistor having a drain connected to the output pad, and a gate connected to the drain of a predriver transistor. The output transistor has a gate-source capacitance characteristic, and the predriver transistor has a predriver time constant above a selected threshold based on the electrical characteristic. The first predriver transistor also has a selected resistance based on the predriver time constant and the gate-source capacitance characteristic, such that the first predriver is operable to switch the output transistor at a sufficiently slow rate to avoid ringing.

Abstract: .[.The invention teaches the uses of a plurality of electric fields and of orthogonal spray configurations of vaporized analyte which combine so as to operate to enhance the efficiency of analyte detection and mass analysis with a mass spectrometer by reducing vapor in the vacuum system and concomitant noise. Several embodiments of the invention are described for purposes of illustration..]. .Iadd.The invention relates to a method and apparatus for improving signal relative to noise without loss of ion collection efficiency in electrospray mass spectrometry, including liquid chromatography/mass spectrometry..Iaddend.