Abstract: Disclosed is an image dehazing method, including: obtaining a second dark channel map corresponding to a target image based on a first dark channel value corresponding to each pixel in the target image; obtaining an atmospheric light value; obtaining a haze intensity value; obtaining a dehazing intensity correction value based on the haze intensity value, a first dark channel value corresponding to each pixel in a first dark channel map, or a brightness value corresponding to each pixel in the target image; obtaining an estimated value of a transmittance based on the dehazing intensity correction value, a second dark channel value corresponding to each pixel in the second dark channel map, and the atmospheric light value; and obtaining an estimated dehazed image based on the estimated value of the transmittance, the target image and the atmospheric light value. Therefore, the generation of the halo effect can be avoided.

Abstract: A projection device and a projection picture correction method thereof are provided. When the projection device performs projection toward a projection surface, a plurality of target coordinates of a plurality of target vertexes are obtained based on a plurality of planes of the projection surface. The plurality of planes are not coplanar with each other, and the plurality of target vertexes form a target polygon. A first direction scaling process is performed respectively on a plurality of first image portions of an original trapezoidal image and a trapezoidal image block is generated. A second direction scaling process is performed respectively on a plurality of second image portions of the trapezoidal image block and a target image block aligned with the target polygon is generated. An output image including the target image block is projected onto the projection surface.

Abstract: The embodiments of the disclosure provide a space recognition method, an electronic device and a non-transitory computer-readable storage medium. The method includes the following steps. Sensor data for detecting obstacle positions is obtained from a sensor associated with an electronic device. A plurality of coordinates respectively corresponding to the obstacle positions are generated based on the sensor data. Boundary line information of a space surrounding the electronic device is updated according to the coordinates until an optimization condition is met for each boundary line. A spatial range of the space surrounding the electronic device is identified based on the boundary line information. The spatial range is used to guide a movement of the electronic device.

Abstract: A voltage regulating device and a mode switching detecting circuit are provided. The mode switching detecting circuit is configured to reset a soft start circuit of the voltage regulating device. The mode switching detecting circuit includes a mode switching signal detector, a reset signal generator, and a reset status detector. The mode switching signal detector receives a mode switching signal and generates a setting signal according to a transition edge of the mode switching signal. The reset signal generator is coupled to the mode switching signal detector and generates a reset activating signal according to the setting signal. The reset activating signal drives the soft start circuit to perform a reset operation. The reset status detector compares an output voltage of the soft start circuit and a reference voltage to generate a clear signal. The reset signal generator clears the reset activating signal according to the clear signal.

Abstract: A projection apparatus and a keystone correction method thereof are provided. The projection apparatus includes a display processing circuit including an image processing circuit, a first keystone correction circuit, a rotation circuit, a second keystone correction circuit, and a video output circuit. The first keystone correction circuit performs first keystone correction processing on a processed image frame based on horizontal scaling processing to obtain a first corrected image frame. The rotation circuit performs rotation processing on the first corrected image frame to write a rotated image frame into a memory. The second keystone correction circuit reads the rotated image frame from the memory and performs second keystone correction processing on the rotated image frame based on the horizontal scaling processing to obtain a second corrected image frame. The video output circuit transmits the second corrected image frame to a projection module through a data transmission interface.

Abstract: A video transmitting circuit and a signal delay compensation method thereof are provided. The video transmitting circuit transmits a specific signal through a first transmission path and a second transmission path to a video receiver during a calibration mode. In the calibration mode, a return detection circuit of the video transmitting circuit detects whether or not a first return signal transmitted through the first transmission path and a second return signal transmitted through the second transmission path have been received by the video transmitting circuit. The video transmitting circuit sets delay circuits serially connected in the first or second transmission path according to a detection result of the return detection circuit, such that the first return signal transmitted through the first transmission path and the second return signal transmitted through the second transmission path can synchronously arrive at the video receiver.

Abstract: A signal receiver and a signal transceiver are provided, which may avoid unnecessary leakage current. The signal receiver includes a termination switch pair, a first resistor, a second resistor, and a pull-down circuit. The termination switch pair receives an operation power supply. The termination switch pair has a common control end. The first resistor is coupled between a first signal input end and the common control end. The second resistor is coupled between a second signal input end and the common control end. The pull-down circuit is coupled between the common control end and a reference voltage end. The pull-down circuit determines whether to pull down a first control voltage on the common control end to a reference voltage according to a power-on state or a power-off state of the signal receiver.

Abstract: The disclosure provides a voltage regulator with a soft-start effect. The voltage regulator includes an amplifier, a first voltage setting circuit, a voltage selector and a power transistor. The amplifier has two input terminals to receive respectively a reference voltage and a feedback voltage. The amplifier has a current source to provide a current to an output terminal. In a voltage bypass mode, the first voltage setting circuit increases a driving voltage on the output terminal according to the current based on a selection voltage. In the voltage bypass mode, the voltage selector sequentially reduces the selection voltage respectively in multiple time intervals in a startup time interval. The power transistor receives the driving voltage, and generates an output voltage according to the driving voltage based on an operating power supply.

Abstract: A voltage regulator including an amplifier, a start signal generator and a power transistor is provided. The amplifier has a first positive input terminal, a second positive input terminal, and a negative input terminal to receive a start signal, a reference voltage and a feedback voltage respectively. An output terminal of the amplifier generates a driving voltage. The start signal generator is coupled to the first positive input terminal of the amplifier and generates the start signal, which is incremental, during a startup time interval in a voltage bypass mode. The power transistor generates an output voltage according to the driving voltage based on an operating power. In the voltage bypass mode, the reference voltage is equal to the operating power. A soft-start effect can be effectively achieved by the voltage regulator in the voltage bypass mode.

Abstract: An electronic device includes a core circuit and a detecting circuit. The core circuit receives a first clock signal and a second clock signal that are different. The core circuit generates a first working state and a second working state respectively according to the first clock signal and the second clock signal. The detecting circuit detects a relationship between the first working state and the second working state to generate a reset signal. The reset signal is configured to reset the relationship between the first working state and the second working state to an initial corresponding relationship, and reduce an influence of electromagnetic interference on the electronic device.

Abstract: A voltage regulator, including an amplifier, a voltage setting circuit and a power transistor, is provided. The amplifier includes a first current source and a second current source. The amplifier has two input terminals to respectively receive a reference voltage and a feedback voltage. The first current source is coupled between the operating power source and an output terminal of the amplifier, and provides a first current to the output terminal. The second current source is coupled between the output terminal and a reference ground terminal, and draws a second current from the output terminal. The voltage setting circuit is coupled to the output terminal, and increases a driving voltage on the output terminal according to the first current in a voltage bypass mode. The power transistor receives the driving voltage and generates an output voltage according to the driving voltage based on the operating power source.

Abstract: A projection device and a projection image correction method are provided. Four target coordinates of four target vertices forming a target quadrilateral boundary are obtained. A first trapezoidal boundary is obtained according to a predetermined image boundary and a first coordinate component of each of the four target coordinates. At least one edge of the target quadrilateral boundary is extended until intersecting with at least one of two reference line segments to obtain a second trapezoidal boundary. Bases of the first trapezoidal boundary are perpendicular to bases of the second trapezoidal boundary. First direction scaling processing is performed according to the first trapezoidal boundary, and second direction scaling processing is performed according to the second trapezoidal boundary, to scale an original image into a target image block aligned with the target quadrilateral boundary in an output image. The projection device projects the output image to display a rectangular projection image.

Abstract: A multi-task deep learning network and a generation method thereof are provided. The generation method of a multi-task deep learning network includes: building at least one shared layer, where the shared layer is configured to receive a plurality of pieces of input information and generate a plurality of pieces of processed feature information; building a plurality of groups of task-specific layers, wherein the groups of task-specific layers compute and generate a plurality of groups of output information corresponding to a plurality of different tasks according to the pieces of processed feature information; and activating at least one of the groups of task-specific layers in stages according to a power supply state of an electronic apparatus.

Abstract: Disclosed is a method for reducing residual echo including: performing an echo cancellation process on a voice input signal according to an echo reference signal to obtain an echo cancellation signal; performing a FFT on the echo reference signal to obtain a reference spectrum signal for each frame; performing the FFT on the echo cancellation signal to obtain a speech spectrum signal for each frame; using the reference spectrum signal and the speech spectrum signal of a current frame to obtain a priori signal-to-noise ratio of the current frame according to a principle of additive noise; filtering the speech spectrum signal of the current frame by a Wiener filter coefficient of the current frame determined by the prior signal-to-noise ratio of the current frame to obtain a target spectrum signal of each frame; performing an IFFT on the target spectrum signal of each frame to obtain a target voice signal.

Abstract: A phase interpolator capable of preventing a glitch from being generated during a clock signal switching operation and a clock signal selector thereof are provided. The clock signal selector includes a selector and a selection signal generator. The selector receives multiple clock signals with different phases. The selector selects one of the clock signals according to a selection signal to generate a selected clock signal. The selection signal generator is coupled to the selector and generates the selection signal. When the selector switches from selecting a first clock signal to selecting a second clock signal as the selected clock signal, the selection signal generator generates a set time point according to a transition point of one of the first clock signal and the second clock signal whose phase lags behind a phase of the other, and generates the selection signal according to the set time point.

Abstract: A deskew circuit for a differential signal is provided. A first common mode voltage generating circuit generates a first common mode voltage signal according to first and second differential input signals. A voltage buffer circuit is coupled to the first common mode voltage generating circuit and has an input impedance higher than a preset value, and buffers the first common mode voltage signal and the first and second differential input signals to generate a second common mode voltage signal, a third differential input signal, and a fourth differential input signal. A second common mode voltage generating circuit is coupled to the voltage buffer circuit and generates a third common mode voltage signal according to the third and fourth differential input signals. An output circuit generates a deskew output signal according to the third and fourth differential input signals and the second and third common mode voltage signals.

Abstract: An electronic package device and a carrier structure thereof are provided. The carrier structure includes a die attach paddle, a ground frame, a pin assembly, and a ground wing portion. The ground frame surrounds the die attach paddle. The pin assembly includes a plurality of pins that are spaced apart from one another. The pins extend radially outward and are arranged to surround the ground frame. The ground wing portion is connected to the ground frame and located in a space under the pin assembly. The ground wing portion includes an extending part and a joint part, the extending part extends away from the die attach paddle, and a top end of the extending part is located at a position above where a bottom surface of the die attach paddle is located.

Abstract: The disclosure provides a video decoding method and a video decoding device. An initial stream is received. In a first flow cycle, entropy decoding is performed on a plurality of first frames in parallel according to the initial stream by a plurality of entropy decoders of a plurality of processing cores, so as to generate a plurality of first decoded streams respectively corresponding to the first frames. In the first flow cycle, a second decoded stream is decoded by a plurality of coding tree unit decoders of the processing cores, so as to reconstruct a second frame.

Abstract: A semantic recognition method and a semantic recognition device are provided. A spectrogram of a speech signal is generated. At least one keyword of the spectrogram is detected by inputting the spectrogram into a neural network model. A semantic category to which each of the at least one keyword belongs is distinguished. A semantic intention of the speech signal is determined according to the at least one keyword and the semantic category of the at least one keyword.

Abstract: The disclosure provides a bias voltage calibration circuit adapted for a signal receiving device. The bias voltage calibration circuit includes a reference voltage generator, a voltage-current converter, and a bias current generator. The reference voltage generator receives a voltage adjustment signal, and adjusts a voltage value of a generated reference voltage according to the voltage adjustment signal. The voltage-current converter is coupled to the reference voltage generator, and converts the reference voltage to generate a reference current. The bias current generator generates a plurality of bias currents according to the reference current, and provides the bias current to an equalization circuit of the signal receiving device in a calibration mode.