Abstract: The invention provides a circuit structure sharing the same memory, where the circuit structure includes a first volatile memory, a system chip and a signal processing chip. The system chip is connected to the first volatile memory via a first connection interface. The signal processing chip is connected to the system chip via a second connection interface. A memory controller is disposed in the system chip and connected to the first connection interface and the second connection interface. The signal processing chip transmits a first access command to the memory controller via the second connection interface, and the memory controller accesses the first volatile memory via the first connection interface according to the first access command and transmits the access result of the first access command to the signal processing chip via the second connection interface.

Abstract: The disclosure provided a tuner circuit having a zero power loop through (ZPLT) circuit that is capable of providing a loop through path even when no power is being supplied or without a standalone power supply. The tuner circuit includes an input terminal, an output terminal, a ZPLT circuit, and an internal resistor. The input terminal receives a radio frequency (RF) signal. The output terminal is connected to a subsequent tuner. The ZPLT is connected between the input terminal and the output terminal. The internal and an external resistor connected between the turner circuit and subsequent tuner form a voltage divider to divide a bias found at the output terminal to enable the ZPLT circuit for providing a loop through path to deliver the RF signal to the output terminal when the tuner circuit is not powered by a standalone power or a low noise amplifier is enabled.

Abstract: The embodiments of the disclosure introduce a novel receiver having a smart listening mode for reducing the current consumption of a receiver while waiting for a data packet. In the smart listening mode, the receiver temporarily disables one signal path of a quadrature signal (e.g., I or Q path) until the receiver detects an arrival of data packet via a second signal path of the quadrature signal. The receiver continuously monitors the enabled signal path for the incoming data packet via in-channel energy. After the incoming data packet is detected, it is further determined whether the incoming data packet is a valid data packet. If not, one of the signal paths would be disabled again. As a result, the current consumption of the receiver is reduced while waiting for an incoming data packet.

Abstract: A packaged circuit including a digital controller, a port physical layer and a digital coding circuit is provided. The digital controller outputs digital data in parallel via a parallel data channel, and the digital data includes a plurality of data bits. The port physical layer includes a clock generator, and outputs a data signal according to the data bits. The clock generator outputs a clock signal to the digital controller. The digital coding circuit is coupled to the digital controller and the port physical layer, and receives the digital data and the clock signal. The digital coding circuit codes the clock signal to generate a plurality of clock bits, and outputs the clock bits to the port physical layer. The port physical layer converts the clock bits into an output clock and outputs the output clock.

Abstract: A terminal circuit and an output stage circuit are provided. The terminal circuit is configured between a transmitter and an external device. The transmitter provides a differential signal to the external circuit. The terminal circuit includes a first to a third switches and a first and a second resistor. The first switch is biased by a first voltage provided by the transmitter. The first and the second resistor receive the differential signal. The second switch is coupled between the first switch and the first resistor. The third switch is coupled between the first switch and the second resistor. The first to the third switches are controlled by a first to a third control signals, respectively. When the transmitter operates in a power-off mode, a voltage level of the first voltage is in ground level, and the first to the third control signals turn off the first to third switches.

Abstract: A network connection device and a cable status detection method are provided. The network connection device is configured to connect and detect a connection cable. The network connection device includes an interface module, a physical layer transmission circuit and a cable status detection module. The interface module connects the connection cable. The physical layer transmission circuit sends signals to the connection cable or receives signals from the connection cable through the interface module. The cable status detection module receives a notification notifying that the physical layer transmission circuit is in a disable state, and detects the status of the connection cable and generates a detection result when the physical layer transmission circuit is in the disable state. In this way, the network connection device may transmit data signals though the connected connection cable and detect the status of the connection cable.

Abstract: A buffer circuit includes a transistor cascode circuit, a latch circuit, a first transistor, a second transistor, and a voltage generator. The transistor cascode circuit is biasing at a first voltage. The latch circuit is biasing at a second voltage, whose voltage level is negative. The first transistor and the second transistor are coupling between the transistor cascode circuit and the latch circuit, and a gate of the first transistor is coupled to a gate of the second transistor. The voltage generator provides a biasing voltage to the gate of the first transistor and adjusts a voltage level of the biasing voltage dynamically according to a voltage level of the second voltage. The biasing voltage is at a first level when the buffer circuit is initially turned on, and the biasing voltage is at a second level when the buffer circuit enters the steady state.

Abstract: An Ethernet physical layer circuit and a clock recovery method are provided. An analog-to-digital converter samples an analog input signal with a sampling clock to generate a digital input signal. A clock generator is coupled to the analog-to-digital converter, outputs the sampling clock to the analog-to-digital converter, and adjusts a phase of the sampling clock according to a phase control signal. The clock recovery circuit is coupled to the analog-to-digital converter and the clock generator, detects a timing error of the digital input signal at refresh stages in a lower energy consumption idle mode to obtain phase adjustment information, and generates the phase control signal based on the phase adjustment information at quiet stages in the low power idle mode. The clock generator correspondingly receives the phase control signal in the quiet stages to adjust the phase of the sampling clock.

Abstract: A vehicle searching system and a method for searching a vehicle are provided. The vehicle searching system includes a vehicle electronic device, a data storage device and a mobile device. The vehicle electronic device captures images along a moving direction of the vehicle, and provides a positioning information of the vehicle and determines whether the vehicle sends a parking stall signal. The data storage device stores data. The mobile device communicates with the data storage device. The vehicle electronic device receives the parking stall signal to select a parking image from the images and obtain positioning information of the vehicle, and transmits the parking image and the positioning information to the data storage device. The mobile device obtains the parking image and the positioning information from the data storage device, and displays the parking image and presents the positioning information in a graphical interface.

Abstract: A WLAN player for synchronizing playing speed includes a speed adjusting module, which is adapted to adjust a speed that the WLAN player plays a medium according to a first playing-progress value and a first clock value of another WLAN player, so as to synchronously play the medium together with said another WLAN player. The WLAN player has a second playing-progress value and a second clock value. The speed adjusting module is configured to calculate a progress difference between the second playing-progress value and the first playing-progress value; calculate a time difference between the second clock value and the first clock value; calculate a specific progress difference according to the progress difference and the time difference; and adjust the speed that the WLAN player plays the medium according to the specific progress difference. In this way, a synchronization error between the WLAN players is effectively decreased.

Abstract: A system on chip (SoC) and a correction method of termination impedance element thereof are provided. The SoC includes a pad, a first termination impedance element, and a correction circuit. The pad is coupled to an external dynamic random access memory (DRAM) chip, where the DRAM chip includes a corrected termination impedance element. The first termination impedance element is coupled to the pad. The correction circuit is coupled to a control terminal of the first termination impedance element, to control an impedance value of the first termination impedance element. During an initialization period, the correction circuit corrects the impedance value of the first termination impedance element by using the impedance value of the corrected termination impedance element.

Abstract: A system on chip (SoC) and a correction method of termination impedance element thereof are provided. The SoC includes a pad, a first termination impedance element, and a correction circuit. The pad is coupled to an external dynamic random access memory (DRAM) chip, where the DRAM chip includes a corrected termination impedance element. The first termination impedance element is coupled to the pad. The correction circuit is coupled to a control terminal of the first termination impedance element, to control an impedance value of the first termination impedance element. During an initialization period, the correction circuit corrects the impedance value of the first termination impedance element by using the impedance value of the corrected termination impedance element.

Abstract: An integrated circuit (IC) and an operation method thereof are provided. The IC includes a first voltage rail, a second voltage rail, an electrostatic discharge (ESD) clamp circuit, a capacitor and a resistive element. A control terminal of the ESD clamp circuit receives a control signal during an ESD period, and the ESD clamp circuit provides an ESD current path between the first voltage rail and the second voltage rail. The capacitor is coupled between the control terminal and the second voltage rail. The resistive element is coupled between the control terminal and the first voltage rail. During a normal operation period, a resistance of the resistive element is a first resistance. During the ESD period, the resistance of the resistive element is a second resistance. The first resistance is smaller than the second resistance.

Abstract: An integrated circuit structure including a reference circuit and at least two core circuits is provided. The reference circuit provides a reference current. The at least two core circuits are coupled to the reference circuit for receiving the reference current. Each of the core circuits includes a current-calibration circuit. The current-calibration circuit generates a bias current according to the reference current in the core circuit. The core circuits use the bias current to replace the reference circuit. In an IC test process, the reference circuit provides the reference current through the pin of the integrated circuit electronically connected to the external impedance. After the IC test process, the connection of the reference circuit and the pin of the integrated circuit is disconnected.

Abstract: The invention relates to a debugging system and a debugging method of a multi-core processor. The debugging system includes a debugging host, a target processor, and a mapping and protocol conversion device. The debugging host includes a debugger, and the target processor includes a plurality of cores. The mapping and protocol conversion device is connected between the debugging host and the target processor, identifies a core architecture to which each of the cores belongs, and maps each of the cores respectively to at least one thread of at least one process according to the core architecture to which each of the cores belongs. Afterwards, the debugger executes a debugging procedure on the target processor according to the process and the thread corresponded to each of the cores.

Abstract: An overvoltage protection device including an output stage, a first switch and a first load providing circuit is provided. The output stage has a first input terminal to receive a first signal, and generates an output signal at an output terminal of the output stage according to the first signal. A first terminal of the first switch is coupled to the first input terminal of the output stage, and a control terminal of the first switch receives a second signal. The first signal is the delayed second signal. The first load providing circuit is coupled to a second terminal of the first switch. The first load providing circuit provides an impedance to the first input terminal when the first switch is turned on.

Abstract: An output circuit includes a level adjustment circuit and a determination circuit. The output circuit is employed for generating an output to an output terminal of the output circuit, where the output terminal is coupled to a connecting port. The level adjustment circuit is coupled to the output terminal and is employed for generating at least one adjusted signal according to a first voltage signal at the output terminal in a first period and a second voltage signal at the output terminal in a second period. The determination circuit is coupled to the level adjustment circuit and is employed for generating a determination signal according to the at least one adjusted signal, wherein the determination signal indicates whether a load is connected to the connecting port.

Abstract: Disclosed are a signal processing method and a signal processing circuit for suppressing Co-Channel Interference (CCI). By using the signal processing method and the signal processing circuit provided by the instant disclosure, determining whether each subcarrier is affected by CCI will be more precise because the non-data subcarrier and the data subcarrier are both processed. Moreover, in the instant disclosure, the results to determine whether the subcarriers are affected by CCI are recorded as an N×K error matrix, and thus the receiver may detect the static interference and the dynamic interference according to this N×K error matrix.

Abstract: A packaged circuit including a digital controller, a port physical layer and a digital coding circuit is provided. The digital controller outputs digital data in parallel via a parallel data channel, and the digital data includes a plurality of data bits. The port physical layer includes a clock generator, and outputs a data signal according to the data bits. The clock generator outputs a clock signal to the digital controller. The digital coding circuit is coupled to the digital controller and the port physical layer, and receives the digital data and the clock signal. The digital coding circuit codes the clock signal to generate a plurality of clock bits, and outputs the clock bits to the port physical layer. The port physical layer converts the clock bits into an output clock and outputs the output clock.

Abstract: An electrostatic discharge (ESD) protection device including an ESD protection unit and a control circuit is provided. When a voltage level of a signal received by a signal input terminal reaches an ESD protection level, the ESD protection unit transmits the signal from the signal input terminal to the system voltage terminal. The control circuit controls a conduction state between the signal input terminal and the system voltage terminal through the ESD protection unit. The control circuit generates a control voltage according to the voltage level of the signal received by the signal input terminal and a system voltage level of the system voltage terminal to control the ESD protection unit, and to prevent the ESD protection unit from transmitting the signal to the system voltage terminal when the voltage level of the signal received by the signal input terminal does not reach the ESD protection level.