Abstract: The disclosure provides a video decoding method and a video decoding device. An initial stream is received. In a first flow cycle, entropy decoding is performed on a plurality of first frames in parallel according to the initial stream by a plurality of entropy decoders of a plurality of processing cores, so as to generate a plurality of first decoded streams respectively corresponding to the first frames. In the first flow cycle, a second decoded stream is decoded by a plurality of coding tree unit decoders of the processing cores, so as to reconstruct a second frame.

Abstract: An image processing device and an image processing method are provided. A frame divider divides an original frame into a plurality of divided blocks. A multi-core circuit coupled to the frame divider and includes a plurality of processing cores and a frame stitching circuit. The processing cores perform an image processing process on the divided blocks to generate a plurality of processed frame blocks. The frame stitching circuit performs an image stitching process according to the processed frame blocks to generate a processed frame. The processing cores fetch the divided blocks and a plurality of extension pixels extending from the divided blocks to perform the image processing process, and a column number of the extension pixels is configured according to a window size requested by at least one window algorithm of the image processing process.

Abstract: A printed circuit board assembly and an electronic apparatus using the same are provided. The printed circuit board assembly includes a circuit board and a first bridging unit. The circuit board includes a first wiring layer, and the first wiring layer includes a plurality of first ground traces, a plurality of first signal traces, and at least one first ground region. Each of the first signal traces is disposed between one of the first ground traces and the first ground region. The first bridging unit is disposed on the first wiring layer of the circuit board. The first bridging unit extends over, without contacting, at least one of the first signal traces from one of the first ground traces to another one of the first ground traces or the first ground region, so as to form at least one first conductive ground path.

Abstract: A semantic recognition method and a semantic recognition device are provided. A spectrogram of a speech signal is generated. At least one keyword of the spectrogram is detected by inputting the spectrogram into a neural network model. A semantic category to which each of the at least one keyword belongs is distinguished. A semantic intention of the speech signal is determined according to the at least one keyword and the semantic category of the at least one keyword.

Abstract: A multistage amplifier for outputting a first output signal includes: an input stage circuit, a middle stage circuit and an output stage circuit. The input stage circuit includes at least one amplifying circuit, which receives the first output signal and a reference signal, thereby to generate a second output signal at an output terminal of the input stage circuit. The middle stage circuit is used to perform frequency compensation on the multistage amplifier. The output stage circuit is used to generate the first output signal at an output terminal of the output stage circuit according to the second output signal. The output stage circuit includes at least one current limiting circuit, where the current limiting circuit is controlled by the second output signal, thereby to adjusting a voltage level of the first output signal.

Abstract: The embodiments of the disclosure provide a space recognition method, an electronic device and a non-transitory computer-readable storage medium. The method includes the following steps. Sensor data for detecting obstacle positions is obtained from a sensor associated with an electronic device. A plurality of coordinates respectively corresponding to the obstacle positions are generated based on the sensor data. Boundary line information of a space surrounding the electronic device is updated according to the coordinates until an optimization condition is met for each boundary line. A spatial range of the space surrounding the electronic device is identified based on the boundary line information. The spatial range is used to guide a movement of the electronic device.

Abstract: A control circuit for controlling signal rising time and falling time is provided. The circuit includes multiple data flip-flops, multiple controllable delay circuits, and multiple current source circuits. The data flip-flops are triggered by clock signals to output a plurality of data signals. The controllable delay circuits delay the data signals, based on corresponding delay amounts, to generate a plurality of activation signals. Each of the current source circuits determines whether to output a unit current to a signal output terminal according to a level of one of the activation signals. Rising or falling time for an output signal of the signal output terminal to rise or fall to a predetermined level is determined according to a cycle time length of the clock signal and the delay amount of each of the controllable delay circuits.

Abstract: The invention discloses a method and a receiving device of the Viterbi algorithm. The method is applicable for a Viterbi decoder that receives an output signal generated by a convolution code encoder processing an original signal. The convolution code encoder includes M registers and M is a positive integer greater than or equal to 2. The method includes the following steps. First, for the first to the Mth data of the output signal, the Viterbi decoder performs the add-compare-select operation based on the known M initial values of the M registers. Then, for the Mth-last to the last data of the output signal, the Viterbi decoder performs the add-compare-select operation based on the known last M bits values of the original signal, thereby reducing the computational complexity of the add-compare-select unit.

Abstract: An interference detection device and a detection sensitivity adjusting method are provided. A signal generating circuit generates a detection signal. A delay circuit delays the detection signal to generate a plurality of delay signals with different delay time. A decision circuit selects one of the delay signals according to a first section signal for comparing with the detection signal to generate an interference detection result, where the delay signals are used for adjusting the detection sensitivity of the interference detection device.

Abstract: The invention provides an integrated circuit (IC) structure including a function circuit and a power ground (P/G) mesh electrically connected with the function circuit. The P/G mesh includes a first metal layer and a second metal layer. The first metal layer and the second metal layer are respectively disposed with a plurality of ground wires and a plurality of power wires. The power wires of the first metal layer are electrically connected with the power wires of the second metal layer through a plurality of first vias, and the ground wires of the first metal layer are electrically connected with the ground wires of the second metal layer through a plurality of second vias. A wire impedance of the first metal layer is different from a wire impedance of the second metal layer. The IC structure can achieve reduction of an IR-drop.

Abstract: A video decoding method and a video decoding device are provided, and the video decoding method includes the following steps. A to-be-decoded bin string is received. A plurality of first current syntax elements in the to-be-decoded bin string are decoded based on a first context model until a decoding output value of the last one of the first current syntax elements matches a specific bin pattern. When the first current syntax elements are decoded, in response to that a state machine is switched from a first decoding operation mode to a second decoding operation mode, a second current syntax element that exists based on the last one of the first current syntax elements is decoded.

Abstract: A wire interconnect structure of an integrated circuit includes a first wiring layer, a second wiring layer, a third wiring layer, a first conductive via structure, a second conductive via structure, and a third conductive via structure. The first wiring layer includes a first wire connected to a first transistor and a second wire connected to a second transistor. The second wiring layer includes a third wire and a fourth wire that are perpendicular to the first wire and the second wire. The third wiring layer includes a fifth wire and a sixth wire that are parallel to the first wire and the second wire and respectively connected to a first contact pad and a second contact pad above. The first transistor is electrically connected to the first contact pad through the first wire, and the second transistor is electrically connected to the second contact pad through the second wire.

Abstract: A control circuit for controlling signal rising time and falling time is provided. The circuit includes multiple data flip-flops, multiple controllable delay circuits, and multiple current source circuits. The data flip-flops are triggered by clock signals to output a plurality of data signals. The controllable delay circuits delay the data signals, based on corresponding delay amounts, to generate a plurality of activation signals. Each of the current source circuits determines whether to output a unit current to a signal output terminal according to a level of one of the activation signals. Rising or falling time for an output signal of the signal output terminal to rise or fall to a predetermined level is determined according to a cycle time length of the clock signal and the delay amount of each of the controllable delay circuits.

Abstract: A channel estimation method and circuit. The channel estimation method, adapted for a receiving device of a multi-input multi-output wireless LAN system, comprises the following steps. Firstly, performing a first channel estimation operation on a long training field to obtain a plurality of first composite channel estimation values related to the long training field. Then, performing a second channel estimation operation on a signal field to obtain a plurality of second composite channel estimation values related to the signal field, and performing a third channel estimation operation on a data segment to obtain a plurality of first channel estimation values related to the data segment. Next, obtaining a plurality of second channel estimation values according to the first composite channel estimation values and the second composite channel estimation values, and adjusting the first channel estimation values related to the data segment according to the second channel estimation values.

Abstract: An object recognition method and system thereof are provided. A recognition result of a first object of a (i?1)th frame of a video stream is obtained. A ith frame is received, and a second object is detected from the ith frame. Whether the first object and the second object are corresponding to the same target object is determined according to a position of the first object in the (i?1)th frame and a position of the second object in the ith frame. If the first object and the second object are corresponding to the same target object, whether a recognition confidence level is greater than a predetermined threshold is determined so as to perform the object recognition on the second object or assign the recognition result of the first object to the second object.

Abstract: The disclosure provides a narrowband filter coupled to a signal path of a first system. The narrowband filter includes a first frequency converter, an integrator, and a second frequency converter coupled to each other in a sequence. The first frequency converter has a first input terminal receiving an input signal from the first system. The narrowband filter also includes a current generator. The current generator has a first terminal coupled to the input signal, a second terminal coupled to a first voltage, and a control terminal coupled to an output terminal of the second frequency converter. The narrowband filter dynamically adjusts a current being drawn from the signal path of the first system, as to detect and eliminate the frequency band of the unwanted signal generated by an influence of a second system close to the first system.

Abstract: The disclosure provides a narrowband filter coupled to a signal path of a first system. The narrowband filter includes a first frequency converter, an integrator, and a second frequency converter coupled to each other in a sequence. The first frequency converter has a first input terminal receiving an input signal from the first system. The narrowband filter also includes a current generator. The current generator has a first terminal coupled to the input signal, a second terminal coupled to a first voltage, and a control terminal coupled to an output terminal of the second frequency converter. The narrowband filter dynamically adjusts a current being drawn from the signal path of the first system, as to detect and eliminate the frequency band of the unwanted signal generated by an influence of a second system close to the first system.

Abstract: An audio signal processing device and an audio signal adjusting method thereof. The audio signal processing device includes a gain determining circuit and an audio signal processing circuit. The gain determining circuit receives an analog audio signal. The gain determining circuit determines a gain based on a difference between a predefined threshold and an amplitude of the analog audio signal in response to detecting that a current sampling amplitude of the analog audio signal is greater than the predefined threshold. The audio signal processing circuit is coupled to the gain determining circuit and receives the analog audio signal and the gain. The audio signal processing circuit attenuates the analog audio signal according to the gain to generate an output audio signal.

Abstract: An interference detection device and a detection sensitivity adjusting method are provided. A signal generating circuit generates a detection signal. A delay circuit delays the detection signal to generate a plurality of delay signals with different delay time. A decision circuit selects one of the delay signals according to a first section signal for comparing with the detection signal to generate an interference detection result, where the delay signals are used for adjusting the detection sensitivity of the interference detection device.

Abstract: A signal receiving device and an equalizer tuning method thereof are provided. A first equalizer receives an input signal and generates a first equalized signal by compensating the input signal according to a first equalization parameter. A second equalizer generates a second equalized signal by compensating the first equalized signal according to a second equalization parameter. A clock and data recovery circuit recovers the second equalized signal to generate an output signal. An equalizing controller receives the input signal and outputs a first control signal and a second control signal, to adjust the first equalization parameter according to the first control signal and adjust the second equalization parameter according to the second control signal. The equalizing controller detects a first pattern symbol and a second pattern symbol from the output signal and tunes the second equalization parameter according to the number of the first pattern symbol and the second pattern symbol.